Digital System Design detail syllabus for Nanoelectronics (Nano), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17NT54), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other nano 5th sem syllabus for be 2017 scheme vtu you can visit Nano 5th Sem syllabus for BE 2017 Scheme VTU Subjects. The detail syllabus for digital system design is as follows.
Course Objectives:
- To design sub systems using combinational circuits and sequential circu
- To design digital systems using CMOS logic and understand the phys digital systems in its transistor schematic form
- To learn Verilog HDL programming and model digital systems using hig its ical structure of h level language
Module 1:
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Module 2:
DESIGNING WITH COMBINATIONAL CIRCUITS: 4-bit Ripple carry adder, 4-bit carry look ahead adder, 4-bit carry select adder, 4-bit comparator using 2-bit comparator, seven segment display controllers using encoders and decoders, parity generators and 3-bit shifters/rotators using multiplexers, barrel shifter/rotator using 2:1 multiplexer Writing Verilog code for 4-bit ripple carry adder, parity generators. 10
Module 3:
DESIGNING WITH SEQUENTIAL CIRCUITS: SR latch, SR-D Latch, T-Latch, flip flops using positive triggered and negative triggered latch, designing N-bit synchronous and asynchronous counters, up-down counters, designing clock dividers using counters, shift registers, SISO, SIPO, PISO, PIPO, 1-bit memory unit with read and write enable, 4-bit memory unit with address decoder. 10
Module 4:
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Module 5:
SUBSYSTEM DESIGN AND MODELLING: writing Verilog code using data flow description for D-latch, JK-flip flop, counters, 2-Bit Magnitude comparators, 4×4 memory with read and write ports, behavioural model for 4-bit ALU design using Verilog HDL, writing test bench wave forms for functional verification of 4-bit adders and ALU Introduction to programmable logics such as PLA, PAL and FPGAs 10
Course Outcomes:
After successfully completing this course, students will be able to understand:
- Fundamental of digital systems
- Design of sub systems using combinational circuits
- Design of sub systems using sequential circuits
- Digital circuit design using MOS transistor
- Apply the Verilog programming skills in modelling digital sub systems
Graduate Attributes (as per NBA):
- Engineering Knowledge.
- Problem Analysis.
- Design / development of solutions (partly).
- Interpretation of data.
Question paper pattern:
- The question paper will have ten questions.
- Each full Question consisting of 20 marks
- There will be 2 full questions (with a maximum of four sub questions) from each module.
- Each full question will have sub questions covering all the topics under a module.
- The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
For Modules 1 – 3 & 5
- N. Botros, HDL programing fundamental: VHDL and Verilog, Cengage learning, 2007
- Thomas L. Floyd, Digital Fundamentals, Pearson Publications, 2012
- John F. Wakerly, Digital Design Principles and Practices, Prentice Hall of India, 2014
- Stephen Brown & Zvonko Vranesic, Fundamentals of Digital Logic Design with Verilog Design, Tata McGraw Hill Edition, 2015 For Module.4
- Neil H. E. Weste & David Money Harris, CMOS VLSI Design: A circuit and systems rd perspective, 3 edition, Pearson Education, 2010
Reference Books:
- Leach D, Malvino A P, Saha G, Digital Principles and Applications, 8/e, McGraw Hill Education, 2015.
- Harris D. M. and, S. L. Harris, Digital Design and Computer Architecture, 2/e, Morgan Kaufmann Publishers, 2013
For detail syllabus of all other subjects of BE Nano, 2017 scheme do visit Nano 5th Sem syllabus for 2017 scheme.
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