Digital System Design detail syllabus for Electrical Engineering (Eee), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17EE35), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other eee 3rd sem syllabus for be 2017 scheme vtu you can visit EEE 3rd Sem syllabus for BE 2017 Scheme VTU Subjects. The detail syllabus for digital system design is as follows.
Course Objectives:
- To impart the knowledge of combinational circuit design.
- To impart the knowledge of Sequential circuit design.
- To provide the basic knowledge about VHDL & its use
Module 1
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Module 2
Analysis and design of Combinational Logic: General approach, Decoders-BCD decoders, Encoders. Digital multiplexers-using multiplexers as Boolean function generators. Adders and Subtractors-Cascading full adders, Look ahead carry, Binary comparators. Design methods of building blocks of combinational logics
Module 3
Sequential Circuits: Basic Bistable element, Latches, SR latch, application of SR latch, A Switch debouncer, The gated SR latch. The gated D Latch, The Master-Slave Flip-Flops (Pulse-Triggered Flip-Flops): The master-slave SR Flip-Flops, The master-slave JK Flip-Flop. Characteristic equations, Registers, Counters-Binary Ripple Counter, Synchronous Binary counters, Counters based on Shift Registers, Design of a Synchronous counters, Design of a Synchronous Mod-6 counters using clocked JK Flip-Flops Design of a Synchronous Mod-6 counter using clocked D, T, or SR FlipFlops
Module 4
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Module 5
HDL: Introduction, A brief history of HDL, Structure of HDL Module, Operators, Data types, Types of Descriptions (only VHDL), Simulation and synthesis, Brief comparison of VHDL and Verilog. Data-Flow Descriptions: Highlights of Data flow descriptions, Structure of data-flow description,
Course Outcomes:
At the end of the course the student will be able to:
- Simplify switching equations generated from truth tables.
- Design combinational logic circuits; adders, Subtractors and comparators.
- Design synchronous sequential circuits; latches, flip-flops, binary counters and Mod –
- Design Mealy and Moore synchronous sequential circuit models.
- Construct state diagrams for sequential circuits.
- Describe the structure of HDL module, operators,data types.
- Give Comparison between VHDL and Verilog.
- Understand the concept of data-flow description 6 counters.
Graduate Attributes (as per NBA):
- Engineering Knowledge,
- Problem Analysis,
- Life-Long Learning,
- Accomplishment of Complex Problems
Question paper pattern:
- The question paper will have ten questions.
- Each full question is for 16 marks.
- There will be 2full questions (with a maximum of four sub questions in one full question) from each module.
- Each full question with sub questions will cover the contents under a module.
- Students will have to answer 5 full questions, selecting one full question from each module
Text Books:
- Digital Logic Applications and John M Yarbrough CengageLearn 2011
- Digital Principles and Design Donald D Givone McGraw Hill 1st Edition, 2002
Reference Books:
- Logic and computer design Fundamentals M. Morries Mano and Charles Kime Pearson Learning 4th Edition, 2014
- Fundamentals of logic design Charles H Roth, JR and Larry L. Kinney Cengage Learning 6th Edition, 2013
- Fundamentals of Digital Circuits A. Anand Kumar PHI 3rd Edition, 2014
- Digital Logic Design and VHDL A.A.Phadke, S.M.Deokar Wiley India 1st Edition, 2009
- Digital Circuits and Design D.P. KothariJ. S.Dhillon Pearson First Print 2015
- HDL Programming (VHDL and Verilog. Nazeih M. Botros Cengage Learning 1st Edition, 2011
- Circuit Design and Simulation with VHDL Volnei A Pedroni PHI 2nd Edition,
For detail syllabus of all other subjects of BE Eee, 2017 scheme do visit Eee 3rd Sem syllabus for 2017 scheme.
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