Digital Electronics detail syllabus for Electronics & Communication Engineering (Ece), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17EC34), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other ece 3rd sem syllabus for be 2017 scheme vtu you can visit ECE 3rd Sem syllabus for BE 2017 Scheme VTU Subjects. The detail syllabus for digital electronics is as follows.
Course Objectives:
This course will enable students to:
- Illustrate simplification of Algebraic equations using Karnaugh Maps and Quine-McClusky Techniques.
- Design combinational logic circuits.
- Design Decoders, Encoders, Digital Multiplexer, Adders, Subtractors and Binary Comparators.
- Describe Latches and Flip-flops, Registers and Counters.
- Analyze Mealy and Moore Models.
- Develop state diagrams Synchronous Sequential Circuits.
Module 1
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Module 2
Analysis and design of combinational logic: General approach to combinational logic design, Decoders, BCD decoders, Encoders, digital multiplexers, Using multiplexers as Boolean function generators, Adders and subtractors, Cascading full adders, Look ahead carry, Binary comparators (Text 1, Chapter 4).
Module 3
Flip-Flops: Basic Bistable elements, Latches, Timing considerations, The master-slave flip-flops (pulse-triggered flip-flops): SR flip-flops, JK flip-flops, Edge triggered flipflops, Characteristic equations. ‘Text 2, Chapter 6’
Module 4
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Module 5
Sequential Circuit Design: Mealy and Moore models, State machine notation, Synchronous Sequential circuit analysis, Construction of state diagram s , counter design. ‘Text 1, Chapter 6’
Course Outcomes:
After studying this course, students will be able to:
- Develop simplified switching equation using Karnaugh Maps and Quine-McClusky techniques.
- Explain the operation of decoders, encoders, multiplexers, demultiplexers, adders, subtractors and comparators.
- Explain the working of Latches and Flip Flops (SR,D,T and JK).
- Design Synchronous/Asynchronous Counters and Shift registers using Flip Flops.
- Develop Mealy/Moore Models and state diagrams for the given clocked sequential circuits.
- Apply the knowledge gained in the design of Counters and Registers.
Text Books:
- Digital Logic Applications and Design, John M Yarbrough, Thomson Learning, 2001. ISBN 981-240-062-1.
- Donald D. Givone, Digital Principles and Design, McGraw Hill, 2002. ISBN 978-007-052906-9.
Reference Books:
- D. P. Kothari and J. S Dhillon, Digital Circuits and Design, Pearson, 2016, ISBN:9789332543539.
- Morris Mano, Digital Design, Prentice Hall of India, Third Edition.
- Charles H Roth, Jr., Fundamentals of logic design, Cengage Learning.
- K. A. Navas, Electronics Lab Manual, Volume I, PHI, 5th Edition, 2015, ISBN: 9788120351424.
For detail syllabus of all other subjects of BE Ece, 2017 scheme do visit Ece 3rd Sem syllabus for 2017 scheme.
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