Digital Design and Hdl detail syllabus for Electronics & Instrumentation Engineering (Eie), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17EI34), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other eie 3rd sem syllabus for be 2017 scheme vtu you can visit EIE 3rd Sem syllabus for BE 2017 Scheme VTU Subjects. The detail syllabus for digital design and hdl is as follows.
Course Objectives:
This course will enable the students to
- To impart the concepts of simplifying Boolean expression using K-map techniques and provide an understanding of logic families
- To impart the concepts of designing and analyzing combinational logic circuits
- To provide an understanding for the concepts of HDL-Verilog, data flow and behavioral models for the design of digital systems.
- To impart design methods and analysis of sequential logic circuits
Module 1
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Module 2
Combinational Functions: Arithmetic Operations: Adders and subtractors-cascading full adders, Look ahead carry, Binary Comparators – 2 bit and 4 bit, two bit Multiplier, Verilog Description of for above circuits. Multiplexers-Realization of 2:1, 4:1 and 8:1 using gates & Applications. Demultiplexers: -Realization of 1:2 1:4 and 1:8 using basic gates & Applications Verilog Behavioral description: Structure, variable assignment statement, sequential statements, loop statements, Verilog behavioral description of Multiplexers (2:1,4:1,8:1) and De-multiplexers (1:2,1:4,1:8.
Module 3
Analysis and design of combinational logic: Encoders: Binary coded decimal codes, Binary – Gray vice versa, BCD – Excess 3 Encoders: Realization and Priority Encoders, Decoders: BCD – Decimal, BCD – Seven segment, Seven segment display. Verilog behavioral description of Encoders (8 to 3 with priority and without priority), Decoders (2 to 4).
Module 4
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Module 5
Counters, design and their applications: Counters-Binary ripple counters, Synchronous binary counters, Modulo N counters – Synchronous and Asynchronous counters. Verilog behavioral description of Synchronous and Asynchronous counters, sequential counters. Synthesis of Verilog: Mapping process in the hardware domain- Mapping of signal assignment, variable assignment, if statements, else-if statements, loop statements
Course Outcomes:
After studying this course, students will able to:
- Simplify Boolean functions using K-map and Quine-McCluskey minimization technique
- Analyze, design and write verilog code for combinational logic circuits. (MUX, De-MUX, adder and subtractor, and comparator circuits)
- Analyze and design code converters, encoders and decoders.
- Analyze and design of synchronous sequential circuits
- Analyze sequential circuits, Moore/Mealy machines
Graduate Attributes (as per NBA):
- Engineering knowledge
- Problem analysis
- Design & Development of Solutions
- Modern tool usage
Question paper pattern:
- The question paper will have TEN questions.
- Each full question consists of 16 marks.
- There will be 2 full questions (with maximum of THREE sub questions) from each module.
- Each full question will have sub questions covering all the topics under a module.
- The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
- Digital Logic Applications and Design by John M Yarbrough, Thomson Learning,2001 (Modules 1,2,3,4,5 -Logic design)
- HDL Programming VHDL and Verilog by Nazeih M. Botros, 2009 reprint, Dreamtech press.(Modules 1,2,3,4,5 Verilog description)
Reference Books:
- Charles H Roth, Jr., Fundamentals of logic design, Cengage Learning
- Digital Principals and Design – Donald D Givone,12th reprint, TMH,2008
- Logic Design, Sudhakar Samuel, Pearson/ Saguine, 2007
- Fundamentals of HDL- Cyril P R Pearson/Sanguin 2010
For detail syllabus of all other subjects of BE Eie, 2017 scheme do visit Eie 3rd Sem syllabus for 2017 scheme.
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