Cad for Vlsi detail syllabus for Electronics & Communication Engineering (ECE), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17EC745), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other ece 7th sem syllabus for be 2017 scheme vtu you can visit ECE 7th Sem syllabus for BE 2017 Scheme VTU Subjects. For all other Professional Elective-3 subjects do refer to Professional Elective-3. The detail syllabus for cad for vlsi is as follows.
Course Objectives:
This course will enable students to:
- Understand various stages of Physical design of VLSI circuits
- Know about mapping a design problem to a realizable algorithm
- Become aware of graph theoretic, heuristic and genetic algorithms
- Compare performance of different algorithms
Module 1
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Module 2
Basic Data Structures. Atomic operations for layout editors, Linked list of blocks, Bin-based method, Neighbor pointers, corner-stitching, Multi-layer operations, Limitations of existing data structures. Layout specification languages. Graph algorithms for physical design: Classes of graphs in physical design, Relationship between graph classes, Graph problems in physical design, Algorithms for Interval graphs, permutation graphs and circle graphs.
Module 3
Partitioning: Problem formulation, Design style specific partitioning problems, Classification of Partitioning Algorithms. Group migration algorithms: Kernighan-Lin algorithm, Fiduccia-Mattheyses Algorithm, Simulated Annealing, Simulated Evolution. Floor Planning: Problem formulation, Constraint based floor planning, Rectangular dualization, Simulated evolution algorithms.
Module 4
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Module 5
Global Routing: Problem formulation, Classification of Global routing algorithms, Maze routing algorithms: Lees algorithm, Soukups algorithm and Hadlocks Algorithm, Line probe algorithms.
Detailed Routing: Problem formulation, Routing considerations, models, channel routing and switch box routing problems. General river routing problem, Single row routing problem.
Two-layer channel routing algorithms: Basic Left Edge Algorithm, Dogleg router, Symbolic router-YACR2.
Course Outcomes:
After studying this course, students will be able to:
- Appreciate the problems related to physical design of VLSI
- Use genralized graph theoretic approach to VLSI problems
- Design Simulated Annealing and Evolutionary algorithms
- Know various approaches to write generalized algorithms
Question paper pattern:
- The question paper will have 10 full questions carrying equal marks.
- Each full question consists of 16 marks with a maximum of Three sub questions.
- There will be 2 full questions from each module covering all the topics of the module
- The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
Algorithms for VLSI Physical Design Automation, 3rd Ed, Naveed Sherwani, 1999 Kluwer Academic Publishers, Reprint 2009 Springer (India) Private Ltd. ISBN 978-81-8128-317-7.
For detail syllabus of all other subjects of BE Ece, 2017 regulation do visit Ece 7th Sem syllabus for 2017 Regulation.
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