Analog and Digital Electronics detail syllabus for Computer Science & Engineering (Cse), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17CS32), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other cse 3rd sem syllabus for be 2017 scheme vtu you can visit CSE 3rd Sem syllabus for BE 2017 Scheme VTU Subjects. The detail syllabus for analog and digital electronics is as follows.
Module 1
Field Effect Transistors: Junction Field Effect Transistors, MOSFETs, Differences between JFETs and MOSFETs, Biasing MOSFETs, FET Applications, CMOS Devices. Wave-Shaping Circuits: Integrated Circuit(IC) Multivibrators. Introduction to Operational Amplifier: Ideal v/s practical Opamp, Performance Parameters, Operational Amplifier Application Circuits:Peak Detector Circuit, Comparator, Active Filters, Non-Linear Amplifier, Relaxation Oscillator, Current-To-Voltage Converter, Voltage-To-Current Converter. Text book 1:- Ch5: 5.2, 5.3, 5.5, 5.8, 5.9, 5.1.Ch13: 13.10.Ch 16: 16.3, 16.4. Ch 17: 7.12, 17.14, 17.15, 17.18, 17.19, 17.20, 17.21..
Module 2
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Module 3
Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder, BCD to Decimal Decoders, Seven Segment Decoders, Encoders, Exclusive-OR Gates, Parity Generators and Checkers, Magnitude Comparator, Programmable Array Logic, Programmable Logic Arrays, HDL Implementation of Data Processing Circuits. Arithmetic Building Blocks, Arithmetic Logic Unit Flip- Flops: RS Flip-Flops, Gated Flip-Flops, Edge-triggered RS FLIP-FLOP, Edge-triggered D FLIP-FLOPs, Edge-triggered JK FLIP-FLOPs. Text book 2:- Ch 4:- 4.1 to 4.9, 4.11, 4.12, 4.14.Ch6:-6.7, 6.10.Ch8:- 8.1 to 8.5.
Module 4
Flip- Flops: FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch Contact Bounce Circuits, Various Representation of FLIP-FLOPs, HDL Implementation of FLIP-FLOP. Registers: Types of Registers, Serial In – Serial Out, Serial In – Parallel out, Parallel In – Serial Out, Parallel In – Parallel Out, Universal Shift Register, Applications of Shift Registers, Register implementation in HDL. Counters: Asynchronous Counters, Decoding Gates, Synchronous Counters, Changing the Counter Modulus. (Text book 2:- Ch 8: 8.6, 8.8, 8.9, 8.10, 8.13. Ch 9: 9.1 to 9.8. Ch 10: 10.1 to 10.4.
Module 5
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Course Outcomes:
After Studying this course, students will be able to,
- Explain the operation of JFETs and MOSFETs, Operational Amplifier circuits and their application Explain Combinational Logic, Simplification Techniques using Karnaugh Maps, Quine McClusky technique. Demonstrate Operation of Decoders, Encoders, Multiplexers, Adders and Subtractors, working of Latches, Flip-Flops, Designing Registers, Counters, A/D and D/A Converters Design of Counters, Registers and A/D & D/A converters
Question paper pattern:
- The question paper will have ten questions.
- There will be 2 questions from each module.
- Each question will have questions covering all the topics under a module.
- The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
- Anil K Maini, Varsha Agarwal: Electronic Devices and Circuits, Wiley, 2012.
- Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital Principles and Applications, 8th Edition, Tata McGraw Hill, 2015
Reference Books:
- Stephen Brown, Zvonko Vranesic: Fundamentals of Digital Logic Design with VHDL, 2nd Edition, Tata McGraw Hill, 2005.
- R D Sudhaker Samuel: Illustrative Approach to Logic Design, Sanguine-Pearson, 2010.
- M Morris Mano: Digital Logic and Computer Design, 10th Edition, Pearson, 2008.
For detail syllabus of all other subjects of BE Cse, 2017 scheme do visit Cse 3rd Sem syllabus for 2017 scheme.
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