18EIL38: Digital Design and Hdl Lab EIE Syllabus for BE 3rd Sem 2018 Scheme VTU

Digital Design and Hdl Lab detailed Syllabus for Electronics & Instrumentation Engineering (EIE), 2018 scheme has been taken from the VTUs official website and presented for the VTU students. For Course Code, Subject Names, Teaching Department, Paper Setting Board, Theory Lectures, Tutorial, Practical/Drawing, Duration in Hours, CIE Marks, Total Marks, Credits and other information do visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the official website of the university.

For all other VTU EIE 3rd Sem Syllabus for BE 2018 Scheme, do visit VTU EIE 3rd Sem Syllabus for BE 2018 Scheme Subjects. The detailed Syllabus for digital design and hdl lab is as follows.

Course Learning Objectives:

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Laboratory Experiments:

1. Simplification, realization of Boolean expressions using logic gates/Universal gates L1,L2,L3
2. To design and implement
   1. Adder/Subtractor – Full/half using logic gates.
   2. 4-bit Parallel Adder/ subtractor using IC 7483. L3, L4, L5,L6
3. To realize
   1. BCD to Excess-3 code conversion and vice versa
   2. Binary to Gray code conversion and vice versa L2,L3, L4
4. To realize
   1. 4:1 Multiplexer using gates
   2. 1:8 Demux
   3. Priority encoder and 3:8 Decoder using IC74138
   4. One / Two bit comparator L2, L3, L4
5. To realize the following flip-flops using NAND Gates
   1. T type
   2. JK Master slave
   3. D type L2, L3, L4
6. To realize the 3-bit counters as a sequential circuit and Mod-N Counter design (7476,7490,74192, 74193) L2, L3, L4
7. Adder/Subtractor – Full/half using Verilog data flow description L2, L3, L4
8. Code converters using Verilog Behavioral description
   1. Gray to binary and vice versa
   2. Binary to excess3 and vice versa L2, L3, L4
9. Multiplexers/decoders/encoder using Verilog Behavioral description
   1. 8:1 mux, 3:8 decoder, 8:3 encoder, Priority encoder
   2. 1:8 Demux and verify using test bench
   3. 2-bit Comparator using behavioral description L2, L3, L4
10. Flip-flops using Verilog Behavioral description
    1. JK type
    2. SR type
    3. T type and
    4. D type L2, L3, L4
11. Counter up/down (BCD and binary) , sequential counters using Verilog Behavioral description L2,L3, L4
12. Interface experiments:
    1. Stepper motor
    2. Relay
    3. Waveform generation using DAC L2,L3, L4

Note:

1. Use discrete components to test and verify the logic gates.
2. Use FPGA/CPLD kits for down loading the Verilog code and test the output.

Course Outcomes:

After studying this course, students will able to:

• Realize Boolean expression using Universal gates / basic gates using ICs and Verilog
• Demonstrate the function of adder/subtractor circuits using gates/ICs & Verilog.
• Design and analyze the Comparator, Multiplexers Decoders, Encoders circuits using ICs and Verilog.
• Design and analysis of different Flip-flops and counters using gates and FFs
• Able to use FPGA/CPLD kits for down loading Verilog codes for shift registers and counters and check output.

Graduate Attributes:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
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Conduct of Practical Examination:

1. All Lab Experiments are to be included for practical examination.
2. Students are allowed to pick one experiment from the lot.
3. Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.
4. Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made zero

Reference Books:

1. Digital Principles and Design – Donald D Givone,12th reprint, TMH,2008
2. HDL Programming VHDL and Verilog By Nazeih M. Botros, 2009 reprint, Dreamtech press.
3. Digital Logic Applications and Design by John M Yarbrough, Thomson Learning,2001
4. Fundamentals of HDL- Cyril P R Pearson/Sanguin 2010

For detail Syllabus of all other subjects of BE 3rd Sem Electronics & Instrumentation Engineering, visit (EIE) 3rd Sem Syllabus Subjects.

For all (CBSE & Non-CBSC) BE results, visit VTU BE all semester results direct links.