18EI34: Digital Design and Hdl EIE Syllabus for BE 3rd Sem 2018 Scheme VTU

Digital Design and Hdl detailed Syllabus for Electronics & Instrumentation Engineering (EIE), 2018 scheme has been taken from the VTUs official website and presented for the VTU students. For Course Code, Subject Names, Teaching Department, Paper Setting Board, Theory Lectures, Tutorial, Practical/Drawing, Duration in Hours, CIE Marks, Total Marks, Credits and other information do visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the official website of the university.

For all other VTU EIE 3rd Sem Syllabus for BE 2018 Scheme, do visit VTU EIE 3rd Sem Syllabus for BE 2018 Scheme Subjects. The detailed Syllabus for digital design and hdl is as follows.

Course Learning Objectives:

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Module -1

Principles of Combinational Logic: Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps- up to 4 variables, Quine-McCluskey Minimization Technique.Quine-McCluskey using Don’t Care Terms. (Text 1, Chapter 3). L2 L3 L4

Module -2

Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices (PLDs), Programmable Read only Memories (PROMS). (Text 2, Chapter 5) L1 L2 L3

Module -3

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Module -4

Simple Flip-Flops Applications: Registers, Binary Ripple Counters, Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using clocked T , JK , D and SR flip-flops. (Text 2, Chapter 6) L2 L3 L4

Module -5

Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of Description- Data flow description, Behavioral description. Implementation of half adder and full adder using Verilog data flow description. Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1,4:1,8:1). (Text 3, Chapters:1, 2, 3) L3 L4 L5

Course Outcomes:

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Graduate Attributes:

(as per NBA)

• Engineering knowledge
• Problem analysis
• Design & Development of Solutions
• Modern tool usage

Question Paper Pattern:

• The question paper will have TEN questions.
• Each full question carry 20 marks
• There will be TWO full questions (with maximum of THREE sub questions) from each module.
• Each full question will have sub questions covering all the topics under a module.
• The students will have to answer FIVE full questions, selecting ONE full question from each module.

Text Books:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
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Reference Books:

1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning
2. Digital Principles and Design – Donald D Givone,12threprint, TMH,2008
3. Logic Design, Sudhakar Samuel, Pearson/ Saguine, 2007
4. Fundamentals of HDL- Cyril P R Pearson/Sanguin 2010

For detail Syllabus of all other subjects of BE 3rd Sem Electronics & Instrumentation Engineering, visit (EIE) 3rd Sem Syllabus Subjects.

For all (CBSE & Non-CBSC) BE results, visit VTU BE all semester results direct links.