3rd Sem, EEE

18EE35: Digital System Design EEE Syllabus for BE 3rd Sem 2018 Scheme VTU

Digital System Design detailed Syllabus for Electrical & Electronics Engineering (EEE), 2018 scheme has been taken from the VTUs official website and presented for the VTU students. For Course Code, Subject Names, Teaching Department, Paper Setting Board, Theory Lectures, Tutorial, Practical/Drawing, Duration in Hours, CIE Marks, Total Marks, Credits and other information do visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the official website of the university.

For all other VTU EEE 3rd Sem Syllabus for BE 2018 Scheme, do visit VTU EEE 3rd Sem Syllabus for BE 2018 Scheme Subjects. The detailed Syllabus for digital system design is as follows.

Course Objectives:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
Get it on Google Play.

Module 1

Principles of Combinational Logic: Definition of combinational logic, canonical forms, Generation of switching equations from truth tables, Karnaugh maps-3,4,5 variables, Incompletely specified functions (Dont care terms) Simplifying Max term equations, Quine-McCluskey minimization technique, Quine-McCluskey using dont care terms, Reduced prime implicants Tables.

Module 2

Analysis and Design of Combinational logic: General approach to combinational logic design, Decoders, BCD decoders, Encoders, digital multiplexers, Using multiplexers as Boolean function generators, Adders and subtractors, Cascading full adders, Look ahead carry, Binary comparators.

Module 3

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
Get it on Google Play.

Module 4

Flip-Flops Applications: Registers, binary ripple counters, synchronous binary counters, Counters based on shift registers, Design of a synchronous counter, Design of a synchronous mod-n counter using clocked T, JK, D and SR flip-flops.

Module 5

Sequential Circuit Design: Mealy and Moore models, State machine notation, Synchronous Sequential circuit analysis, Construction of state diagrams, counter design.
Memories: Read only and Read/Write Memories, Programmable ROM, EPROM, Flash memory.

Course Outcomes:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
Get it on Google Play.

Question paper pattern:

  • The question paper will have ten questions.
  • Each full question is for 20 marks.
  • There will be 2 full questions (with a maximum of three sub questions in one full question) from each module.
  • Each full question with sub questions will cover the contents under a module.
  • Students will have to answer 5 full questions, selecting one full question from each module.

Text Books:

  1. Digital Logic Applications and Design, John M Yarbrough, Thomson Learning 2001 ISBN 981240-062-1.
  2. Digital Principles and Design Donald D. Givone McGraw Hill 2002 ISBN 978-007-052906-9.

Reference Books:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
Get it on Google Play.

For detail Syllabus of all other subjects of BE 3rd Sem Electrical & Electronics Engineering, visit (EEE) 3rd Sem Syllabus Subjects.

For all (CBSE & Non-CBSC) BE results, visit VTU BE all semester results direct links.

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