18EC735: Dsp Algorithms &Architecture ECE Syllabus for BE 7th Sem 2018 Scheme VTU (Professional Elective-2)

Dsp Algorithms &Architecture detailed Syllabus for Electronics & Communication Engineering (ECE), 2018 scheme has been taken from the VTUs official website and presented for the VTU students. For Course Code, Subject Names, Teaching Department, Paper Setting Board, Theory Lectures, Tutorial, Practical/Drawing, Duration in Hours, CIE Marks, Total Marks, Credits and other information, visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the official website of the university.

For all the other VTU ECE 7th Sem Syllabus for BE 2018 Scheme, visit Electronics & Communication Engineering 7th Sem 2018 Scheme.

For all the (Professional Elective-2) subjects refer to Professional Elective-2 Scheme. The detail syllabus for dsp algorithms &architecture is as follows.

Course Learning Objectives:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
.

Module -1

Introduction to Digital Signal Processing: Introduction, A Digital Signal – Processing System, The Sampling Process, Discrete Time Sequences, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Linear Time-Invariant Systems, Digital Filters, Decimation and Interpolation. Computational Accuracy in DSP Implementations: Number Formats for Signals and Coefficients in DSP Systems, Dynamic Range and Precision, Sources of Error in DSP Implementation. L1,L2

Module -2

Architectures for Programmable Digital Signal – Processing Devices: Introduction, Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution, Speed Issues, Features for External Interfacing. L1,L2

Module -3

Module -4

Implementation of Basic DSP Algorithms: Introduction, The Q – notation, FIR Filters, IIR Filters, Interpolation and Decimation Filters (one example in each case). Implementation of FFT Algorithms: Introduction, An FFT Algorithm for DFT Computation, Overflow and Scaling, Bit – Reversed Index. Generation & Implementation on the TMS32OC54xx. L1,L2

Module -5

Interfacing Memory and Parallel I/O Peripherals to Programmable DSP Devices: Introduction, Memory Space Organization, External Bus Interfacing Signals. Memory Interface, Parallel I/O Interface, Programmed I/O, Interrupts and I/O Direct Memory Access (DMA). Interfacing and Applications of DSP Processors: Introduction, Synchronous Serial Interface, A CODEC Interface Circuit, DSP Based Bio-telemetry Receiver, A Speech Processing System, An Image Processing System. L1,L2

Course Outcomes:

Question Paper Pattern:

Examination will be conducted for 100 marks with question paper containing 10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the module.
Students will have to answer 5 full questions, selecting one full question from each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60

Text Books:

Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.

Reference Books:

For the detail Syllabus of all other subjects of BE (ECE) 7th Sem, visit Electronics & Communication Engineering 7th Sem Subjects.

For all (CBSE & Non-CBSC) BE/B.Tech results, visit VTU BE/B.Tech all semester results.

InI KA