18EC72: Vlsi Design ECE Syllabus for BE 7th Sem 2018 Scheme VTU

Vlsi Design detailed Syllabus for Electronics & Communication Engineering (ECE), 2018 scheme has been taken from the VTUs official website and presented for the VTU students. For Course Code, Subject Names, Teaching Department, Paper Setting Board, Theory Lectures, Tutorial, Practical/Drawing, Duration in Hours, CIE Marks, Total Marks, Credits and other information do visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the official website of the university.

For all other VTU ECE 7th Sem Syllabus for BE 2018 Scheme, do visit VTU ECE 7th Sem Syllabus for BE 2018 Scheme Subjects. The detailed Syllabus for vlsi design is as follows.

Course Learning Objectives:

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Module-1

Introduction: A Brief History, MOS Transistors, CMOS Logic (1.1 to 1.4 of TEXT2) MOS Transistor Theory: Introduction, Long-channel I-V Characteristics, Non-ideal I-V Effects, DC Transfer Characteristics (2.1, 2.2, 2.4 and 2.5 of TEXT2). L1, L2

Module-2

Fabrication: CMOS Fabrication and Layout, VLSI Design Flow, Introduction, CMOS Technologies, Layout Design Rules, (1.5 and 3.1 to 3.3 of TEXT2). MOSFET Scaling and Small-Geometry Effects, MOSFET Capacitances (3.5 to 3.6 of TEXT1) L1, L2,

Module-3

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Module-4

Sequential Circuit Design: Introduction, Circuit Design for Latches and Flip-Flops (10.1 and 10.3.1 to 10.3.4 of TEXT2) Dynamic Logic Circuits: Introduction, Basic Principles of Pass Transistor Circuits, Synchronous Dynamic Circuit Techniques, Dynamic CMOS Circuit Techniques (9.1, 9.2, 9.4 to 9.5 of TEXT1) L1, L2, L3

Module-5

Semiconductor Memories: Introduction, Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), (10.1 to 10.3 of TEXT1) Testing and Verification: Introduction, Logic Verification Principles, Manufacturing Test Principles, Design for testability (15.1, 15.3, 15.5 15.6.1 to 15.6.3 of TEXT 2). L1, L2

Course Outcomes:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
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Question Paper Pattern:

• Examination will be conducted for 100 marks with question paper containing 10 full questions, each of 20 marks.
• Each full question can have a maximum of 4 sub questions.
• There will be 2 full questions from each module covering all the topics of the module.
• Students will have to answer 5 full questions, selecting one full question from each module.
• The total marks will be proportionally reduced to 60 marks as SEE marks is 60

Text Books:

1. CMOS Digital Integrated Circuits: Analysis and Design – Sung Mo Kang & Yosuf Leblebici, Third Edition, Tata McGraw-Hill.
2. CMOS VLSI Design- A Circuits and Systems Perspective- Neil H. E. Weste, and David Money Harris4th Edition, Pearson Education.

Reference Books:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
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For detail Syllabus of all other subjects of BE 7th Sem Electronics & Communication Engineering, visit (ECE) 7th Sem Syllabus Subjects.

For all (CBSE & Non-CBSC) BE results, visit VTU BE all semester results direct links.