Digital System Design Using Verilog detailed Syllabus for Electronics & Communication Engineering (ECE), 2018 scheme has been taken from the VTUs official website and presented for the VTU students. For Course Code, Subject Names, Teaching Department, Paper Setting Board, Theory Lectures, Tutorial, Practical/Drawing, Duration in Hours, CIE Marks, Total Marks, Credits and other information, visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the official website of the university.
For all the other VTU ECE 6th Sem Syllabus for BE 2018 Scheme, visit Electronics & Communication Engineering 6th Sem 2018 Scheme.
For all the (Professional Elective-1) subjects refer to Professional Elective-1 Scheme. The detail syllabus for digital system design using verilog is as follows.
Course Learning Objectives:
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Module -1
Introduction and Methodology: Digital Systems and Embedded Systems, Real-World Circuits, Models, Design Methodology (1.1, 1.3 to 1.5 of Text). Combinational Basics: Combinational Components and Circuits, Verification of Combinational Circuits (2.3 and 2.4 of Text). Number Basics: Unsigned integers, Signed Integers, Fixed point Numbers, Floating point Numbers (3.1.1, 3.2.1, 3.3.1 and 3.4). Sequential Basics: Sequential Datapaths and Control Clocked Synchronous Timing Methodology (4.3 up to 4.3.1, 4.4 up to 4.4.1 of Text). L1,L2, L3
Module -2
Memories: Concepts, Memory Types, Error Detection and Correction (Chap 5 of Text). L1,L2, L3
Module -3
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Module -4
I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial Transmission, I/O software (Chap 8 of Text). L1,L2, L3
Module -5
Design Methodology: Design flow, Design optimization, Design for test, Nontechnical Issues (Chap 10 of Text). L1,L2, L3, L4
Course Outcomes:
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Question Paper Pattern:
- Examination will be conducted for 100 marks with question paper containing 10 full questions, each of 20 marks.
- Each full question can have a maximum of 4 sub questions.
- There will be 2 full questions from each module covering all the topics of the module.
- Students will have to answer 5 full questions, selecting one full question from each module.
- The total marks will be proportionally reduced to 60 marks as SEE marks is 60
Text Books:
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using VERILOG, Elesvier, 2010.
Reference Books:
For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
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For the detail Syllabus of all other subjects of BE (ECE) 6th Sem, visit Electronics & Communication Engineering 6th Sem Subjects.
For all (CBSE & Non-CBSC) BE/B.Tech results, visit VTU BE/B.Tech all semester results.