18EC56: Verilog Hdl ECE Syllabus for BE 5th Sem 2018 Scheme VTU

Verilog Hdl detailed Syllabus for Electronics & Communication Engineering (ECE), 2018 scheme has been taken from the VTUs official website and presented for the VTU students. For Course Code, Subject Names, Teaching Department, Paper Setting Board, Theory Lectures, Tutorial, Practical/Drawing, Duration in Hours, CIE Marks, Total Marks, Credits and other information do visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the official website of the university.

For all other VTU ECE 5th Sem Syllabus for BE 2018 Scheme, do visit VTU ECE 5th Sem Syllabus for BE 2018 Scheme Subjects. The detailed Syllabus for verilog hdl is as follows.

Course Learning Objectives:

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Module 1

Overview of Digital Design with Verilog HDL: Evolution of CAD, emergence of HDLs, typical HDL-flow, why Verilog HDL?, trends in HDLs. Hierarchical Modeling Concepts: Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block. L1,L2,L 3

Module 2

Basic Concepts: Lexical conventions, data types, system tasks, compiler directives. Modules and Ports: Module definition, port declaration, connecting ports, hierarchical name referencing. L1,L2,L 3

Module 3

Module 4

Behavioral Modeling: Structured procedures, initial and always, blocking and non-blocking statements, delay control, generate statement, event control, conditional statements, Multiway branching, loops, sequential and parallel blocks. Tasks and Functions: Differences between tasks and functions, declaration, invocation, automatic tasks and functions. L1,L2,L 3

Module 5

Useful Modeling Techniques: Procedural continuous assignments, overriding parameters, conditional compilation and execution, useful system tasks. Logic Synthesis with Verilog: Logic Synthesis, Impact of logic synthesis, Verilog HDL Synthesis, Synthesis design flow, Verification of Gate-Level Netlist. (Chapter 14 till 14.5 of Text). L1,L2,L 3

Course Outcomes:

Question Paper Pattern:

Examination will be conducted for 100 marks with question paper containing 10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the module.
Students will have to answer 5 full questions, selecting one full question from each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60

Text Books:

Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Pearson Education, Second Edition.

Reference Books:

For detail Syllabus of all other subjects of BE 5th Sem Electronics & Communication Engineering, visit (ECE) 5th Sem Syllabus Subjects.

For all (CBSE & Non-CBSC) BE results, visit VTU BE all semester results direct links.

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