Digital System Design detailed Syllabus for Electronics & Telecommunication Engineering (ETE), 2018 scheme has been taken from the VTUs official website and presented for the VTU students. For Course Code, Subject Names, Teaching Department, Paper Setting Board, Theory Lectures, Tutorial, Practical/Drawing, Duration in Hours, CIE Marks, Total Marks, Credits and other information do visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the official website of the university.
For all other VTU ETE 3rd Sem Syllabus for BE 2018 Scheme, do visit VTU ETE 3rd Sem Syllabus for BE 2018 Scheme Subjects. The detailed Syllabus for digital system design is as follows.
Course Learning Objectives:
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Module – 1
Principles of combinational logic: Definition of combinational logic, canonical forms, Generation of switching equations from truth tables, Karnaugh maps-3,4,5 variables, Incompletely specified functions (Dont care terms) Simplifying Max term equations, Quine-McClusky techniques – 3 & 4 variables. (Text 1 -Chapter 3)
Module – 2
Analysis and design of combinational logic: Decoders, Encoders, Digital multiplexers, Adders and subtractors, Look ahead carry, Binary comparators.(Text 1 – Chapter 4). Programmable Logic Devices, Complex PLD, FPGA. (Text 3 – Chapter 9, 9.6 to 9.8)
Module -3
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Module -4
Sequential Circuit Design: Design of a synchronous counter,Design of a synchronous mod-n counter using clockedJK, D, T and SR flip-flops. (Text 2 – Chapter 6) Mealy and Moore models, State machine notation, Construction of state diagrams.(Text 1 – Chapter 6)
Module -5
Applications of Digital Circuits: Design of a Sequence Detector, Guidelines for construction of state graphs, Design Example – Code Converter, Design of Iterative Circuits (Comparator), Design of Sequential Circuits using ROMs and PLAs,CPLDs and FPGAs, Serial Adder with Accumulator, Design of Binary Multiplier, Design of Binary Divider. (Text 3 – 14.1, 14.3, 16.2, 16.3, 16.4, 18.1, 18.2, 18.3)
Course Outcomes:
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Question Paper Pattern:
- Examination will be conducted for 100 marks with question paper containing 10 full questions, each of 20 marks.
- Each full question can have a maximum of 4 sub questions.
- There will be 2 full questions from each module covering all the topics of the module.
- Students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
- John M Yarbrough,-Digital Logic Applications and Design, Thomson Learning,2001.
- Donald D. Givone, Digital Principles and Design!, McGraw Hill, 2002.
- Charles H Roth Jr., Larry L. Kinney Fundamentals of Logic Design, CengageLearning, 7th Edition.
Reference Books:
For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
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For detail Syllabus of all other subjects of BE 3rd Sem Electronics & Telecommunication Engineering, visit (ETE) 3rd Sem Syllabus Subjects.
For all (CBSE & Non-CBSC) BE results, visit VTU BE all semester results direct links.