18CS33: Analog and Digital Electronics IS Syllabus for BE 3rd Sem 2018 Scheme VTU

Analog and Digital Electronics detailed Syllabus for Information Science Engineering (IS), 2018 scheme has been taken from the VTUs official website and presented for the VTU students. For Course Code, Subject Names, Teaching Department, Paper Setting Board, Theory Lectures, Tutorial, Practical/Drawing, Duration in Hours, CIE Marks, Total Marks, Credits and other information do visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the official website of the university.

For all other VTU IS 3rd Sem Syllabus for BE 2018 Scheme, do visit VTU IS 3rd Sem Syllabus for BE 2018 Scheme Subjects. The detailed Syllabus for analog and digital electronics is as follows.

Course Learning Objectives:

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Module 1

Photodiodes, Light Emitting Diodes and Optocouplers ,BJT Biasing :Fixed bias ,Collector to base Bias , voltage divider bias, Operational Amplifier Application Circuits: Multivibrators using IC-555, Peak Detector, Schmitt trigger, Active Filters, Non-Linear Amplifier, Relaxation Oscillator, Current-to-Voltage and Voltage-to-Current Converter , Regulated Power Supply Parameters, adjustable voltage regulator ,D to A and A to D converter. -Text Book 1 :Part A:Chapter 2(Section 2.9,2.10,2.11), Chapter 4(Section 4.2 ,4.3,4.4),Chapter 7 (section (7.2,7.3.1,7.4,7.6 to 7.11), Chapter 8 (section (8.1,8.5), Chapter 9 RBT: L1, L2

Module 2

Karnaugh maps: minimum forms of switching functions, two and three variable Karnaugh maps, four variable karnaugh maps, determination of minimum expressions using essential prime implicants, Quine-McClusky Method: determination of prime implicants, The prime implicant chart, petricks method, simplification of incompletely specified functions, simplification using map-entered variables -Text book 1:Part B: Chapter 5 ( Sections 5.1 to 5.4) Chapter 6(Sections 6.1 to 6.5) RBT: L1, L2

Module 3

Module 4

Introduction to VHDL: VHDL description of combinational circuits, VHDL Models for multiplexers, VHDL Modules. Latches and Flip-Flops: Set Reset Latch, Gated Latches, Edge-Triggered D Flip Flop 3,SR Flip Flop, J K Flip Flop, T Flip Flop, Flip Flop with additional inputs, Asynchronous Sequential Circuits -Text book 1:Part B: Chapter 10(Sections 10.1 to 10.3),Chapter 11 (Sections 11.1 to 11.9) RBT: L1, L2

Module 5

Registers and Counters: Registers and Register Transfers, Parallel Adder with accumulator, shift registers, design of Binary counters, counters for other sequences, counter design using SR and J K Flip Flops, sequential parity checker, state tables and graphs -Text book 1:Part B: Chapter 12(Sections 12.1 to 12.5),Chapter 13(Sections 13.1,13.3 RBT: L1, L2

Course Outcomes:

Question Paper Pattern:

The question paper will have ten questions.
Each full Question consisting of 20 marks
There will be 2 full questions (with a maximum of four sub questions) from each module.
Each full question will have sub questions covering all the topics under a module.
The students will have to answer 5 full questions, selecting one full question from each module.

Textbooks:

Charles H Roth and Larry L Kinney, Analog and Digital Electronics, Cengage Learning,2019

Reference Books:

For detail Syllabus of all other subjects of BE 3rd Sem Information Science Engineering, visit (IS) 3rd Sem Syllabus Subjects.

For all (CBSE & Non-CBSC) BE results, visit VTU BE all semester results direct links.

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