15EC65P: Verilog Lab Electronics 6th Sem Syllabus for Diploma DTE Karnataka C15 Scheme

Verilog Lab detail DTE Kar Diploma syllabus for Electronics And Communication Engineering (EC), C15 scheme is extracted from DTE Karnataka official website and presented for diploma students. The course code (15EC65P), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below. The syllabus PDFs can be downloaded from official website.

For all other electronics 6th sem syllabus for diploma c15 scheme dte karnataka you can visit Electronics 6th Sem Syllabus for Diploma C15 Scheme DTE Karnataka Subjects. The detail syllabus for verilog lab is as follows.

Pre-requisites:

Knowledge of basic Mathematics, digital electronic circuits and Programming languages.

Course Objectives:

Learn and understand the basics of Hardware description language and its use in designing electronic circuits.

Course Outcomes:

For complete syllabus and results, class timetable and more pls download iStudy Syllabus App. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

UNIT – 1: Tutorial and Practice Duration: 24 Hrs

1. Evolution of Computer-Aided digital design, Introduction to HDL, Importance of HDL, levels of abstraction, typesof code-Structural and procedural. 3
2. Introduction to Verilog HDL, Definition, Program Structure of Verilog, Lexical Tokens/Conventions-explain with syntax-White Space, Comments, Numbers, Identifiers, Operators, Verilog Keywords. Data types-explain with syntax-Value Set, Wire, Reg, Input, Output, Inout Integer, Supply0, Supply1, Time, Parameter. Simple examples. 3
3. Operators with examples-Arithmetic, Logical, Relational, Bit-wise, Reduction, Shift, concatenation, Replication, Conditional operators. Operator Precedence. 3
4. Operands-explain with syntax-Literals, Wires, Regs, and Parameters, BitSelects, Part-Selects, Function Calls. Simple examples. 3
5. Modules-Module Declaration, Continuous Assignment, Module Instantiations, Parameterized Modules, Procedures: Always and Initial Blocks. Simple examples. 3
6. Tasks and Functions-display, strobe, monitor, reset, stop, finish etc. Timing Control-Delay Control(#), Events, wait Statement, join Statements. 3
7. Behavioral Modeling-Procedural Assignments, Delay in Assignment, Blocking Assignments, Non-blocking (RTL) Assignments, begin .. end, for Loops, while Loops, forever Loops, if .. else if .. else, disable, case. Simple examples. 3
8. Functions-Function Declaration, Return Value, Call, Function Rules, Simple Examples. Brief description about Gate-Level Modeling,Dataflow Modeling, Switch-Level Modeling. 3

Practice Exercises

Write and execute verilog code for the following problems

1. Verilog Description for all two input basic gates.
2. Verilog Description for two input Arithmetic operations.
3. Verilog Description for three/four input Logical operations.
4. Compute the output for arithmetic expression. y=(a+b*c)/(a+c)
5. Compute the output for Logical expression. y= (A and B) or (B and C).
6. Verilog Description for 1-bit Full Adder
7. Verilog Description for 2:1 multiplexer using dataflow/behavioral method.
8. Verilog Description for 1:2 De-multiplexer using dataflow/behavioral method.
9. Verilog Description for 2-bit parallel adder.
10. Verilog Description for 2-bit ALU with any 2 arithmetic and logical operations.
11. Verilog Code for D-flipflop
12. Verilog Code for T-flipflop
13. Verilog Description for mod-6 counter.

UNIT – 2: Graded Exercises Duration: 48 Hr

Write the verilog code for the following problems and simulate using any HDL simulator/synthesis software (Xilinx/Modelsim/Simulink etc) and download to FPGA/CPLD trainerkits.

1. Verilog description for full-adder using structural modeling.
2. Verilog description for full-adder using behavioral modeling. 3
2. Verilog description for 4-bit ripple carry full-adder using 1-bit full-adder. 3
1. Verilog description for BCD to seven segment decoder for common anode display using if else.
2. Verilog description for BCD to seven segment decoder using case statement. 3
1. Verilog description for 4 -bit parallel adder.
2. Verilog description for 4-bit comparator. 3
1. Verilog description for 4-bit ALU with threelogical & three arithmetic operations.
2. Verilog description for any threerelational and three bit-wise operations. 3
1. Verilog description for 4-to-1 multiplexer using logic equations.
2. Verilog description for 4-to-1 multiplexer using conditional operators.
3. Verilog description for 4-to-1 multiplexer using behavioral modeling.
4. Verilog description for 4-to-1 multiplexer using 2:1 muxes. 6
1. Verilog description for clocked T-flip flop.
2. Verilog description for edge-triggered D-flip flop. 3
1. Verilog description for edge-triggered JK-flip flop.
2. Verilog description for 4-bit counter using JK-flip flop. 6
1. Verilog description for BCD up/down counter using behavior modeling.
2. Verilog description for 4-bit ripple carry counter using T and D-flip flop. 3
10. Verilog description for universal shift register. 3
11. Two open-ended experiments of similar nature as above are to be assigned by the teacher. Student is expected to solve and execute/simulate independently using verilog code. 6

Unit – 3: Student Activities [CIE- 05 Marks] 06 Hours & off-classes

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Reference Books:

1. Fundamentals of Digital logic with Verilog design-2e, Brown Vranesic, McGrawHill education, ISBN-13:978-0-07-066724-2.
2. Verilog HDL-A guide to Digital Design and Synthesis-Samir Palnitkar-ISBN: 0134516753; Pub: Prentice Hall PTR.
3. Introduction to Verilog-.Peter M. Nyasulu.
4. Handbook on Verilog HDL-Dr. Daniel C. Hyde,Bucknell University
5. Verilog Tutorial – Deepak Kumar Tala
6. The Verilog Hardware Description Language-Donald Thomas and Philip Moorby (2008)
7. http://www.iitk.ac.in/eclub/summercamp/Courses/CompArch/Verilog lab Solutions.pdf
8. http://users.ece.utexas.edu/~ljohn/teaching/ee460m lab manual.pdf
9. http://treymorris.com/classes/elen/248/lab/lab%20manuals/lab manual 5.pdf
10. http://d1.amobbs.com/bbs upload782111/files 33/ourdev 585395BQ8J9A.pdf
11. www.cc.gatech.edu/~hadi/../01../verilog/An%20Introduction%20to%20Verilog.pdf
12. www.ece.niu.edu.tw/~chu/download/fpga/verilog.pdf
13. http://www.asic-world.com/
14. https://www.youtube.com/watch?v=QSEl O0Gtoo&list=PLoM0uG7tqR3qVss3zhBRniXU7mhHy2bwj

Course Delivery:

The course will be normally delivered through two-hour tutorials and four-hour hands-on practice per week; hands-on practice shall include verilog simulation programs. Normally, one-hour tutorial followed by two-hour hands-on practice is recommended in each class. Tutorial shall be imparted before the conduction of the experiment. However, activities are carried-out off-class and demonstration/presentation can be in lab sessions.

Student Activity (5 marks):

For complete syllabus and results, class timetable and more pls download iStudy Syllabus App. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

Execution Notes:

1. Each batch of 2 students is assigned at least one activity listed in Unit-3 based on interest of the students. Student can also choose any other similar /relevant activity with prior approval from the concerned teacher.
2. Teacher is expected to observe and record the progress of students activities
3. Assessment is made based on quality of work as prescribed by the table

Model Questions for Practice and Semester End Examination

Note: The questions in the question bank are indicative but not exhaustive.

1. Write a verilog code for half-adder and full-adder using behavioral modelling.
2. Write a verilog code for half-subtractor and full-subtractor using behavioural modeling.
3. Write a verilog code for 4-bit full-adder, Using Dataflow Operators.
4. Write a verilog code for 4 bit parallel adder.
5. Write a verilog code for BCD to seven segment decoder.
6. Write a verilog code for 4 bit parallel adder.
7. Write a verilog codefor 4 bit comparator.
8. Write a verilog codefor 4-to-1 multiplexer, using logic equations.
9. Write a verilog codefor 4-to-1 multiplexer, using conditional operators.
10. Write a verilog codefor behavioral 4-to-1 multiplexer.
11. Write a verilog codefor1:4 de-multiplexer, using logic equations.
12. Write a verilog codefor1:4 de-multiplexer using behavioralmodeling.
13. Write a verilog code for clocked T-flipflop.
14. Write a verilog code for edge-triggered D-flipflop.
15. Write a verilog code for edge-triggered JK-flipflop
16. Write a verilog code forripple counter
17. Write a verilog code forbehavioral 4-bit counter.
18. Write a verilog code foruniversal shift register/left-right shifter using function.
19. Write a Switch-level verilogdescription of 2-to-1 multiplexer.
20. Write a Switch-level verilogdescription of CMOS inverter.
21. Write a Switch-level verilog for NOR-gate
22. Write a verilog code for 4-bit ALU with 3 logical & 3 arithmetic operations
23. Write a verilog code for any 2 relational and 2-bit-wise operations

For detail syllabus of all other subjects of BE Electronics, C15 scheme do visit Electronics 6th Sem syllabus for C15 scheme.

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