{"id":4610,"date":"2020-02-08T06:40:07","date_gmt":"2020-02-08T06:40:07","guid":{"rendered":"https:\/\/www.inspirenignite.com\/up\/vlsi-design-ee-7th-sem-syllabus-for-aktu-b-tech-2019-20-scheme\/"},"modified":"2020-07-20T08:19:13","modified_gmt":"2020-07-20T08:19:13","slug":"vlsi-design-ee-7th-sem-syllabus-for-aktu-b-tech-2019-20-scheme","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/up\/vlsi-design-ee-7th-sem-syllabus-for-aktu-b-tech-2019-20-scheme\/","title":{"rendered":"Vlsi Design EE 7th Sem Syllabus for AKTU B.Tech 2019-20 Scheme"},"content":{"rendered":"

Vlsi Design detail syllabus for Electronics Engineering (Ee), 2019-20 scheme is taken from AKTU<\/a> official website and presented for AKTU students. The course code (REC702), and for exam duration, Teaching Hr\/Week, Practical Hr\/Week, Total Marks, internal marks, theory marks, duration, and credits do visit complete sem subjects post given below.<\/p>\n

For all other ee 7th sem syllabus for b.tech 2019-20 scheme aktu you can visit EE 7th Sem syllabus for B.Tech 2019-20 Scheme AKTU Subjects<\/a>. The detail syllabus for vlsi design is as follows.<\/p>\n

Unit I<\/h4>\n

For the complete syllabus, results, class timetable and more kindly download iStudy<\/a>. It’s a lightweight, easy to use, no images, no pdfs platform to make student’s life easier.<\/b><\/p>\n

Unit II<\/h4>\n

Delay: Introduction, Transient Response, RC delay model, Linear Delay Model, Logical Effort of Paths, Timing Analysis Delay Models. Power: Introduction, Dynamic Power, Static Power<\/p>\n

Unit III<\/h4>\n

Energy-Delay Optimization, Low Power Architectures. Interconnect: Introduction, Interconnect Modelling, Interconnect Impact, Interconnect Engineering, Logical Effort with Wires<\/p>\n

Unit IV<\/h4>\n

For the complete syllabus, results, class timetable and more kindly download iStudy<\/a>. It’s a lightweight, easy to use, no images, no pdfs platform to make student’s life easier.<\/b><\/p>\n

Unit V<\/h4>\n

Low-Power CMOS Logic Circuits: Introduction, Overview of Power Consumption, Low-Power Design through voltage scaling, Estimation and Optimization of switching activity, Reduction of Switched Capacitance and Adiabatic Logic Circuits. Design for Testability: Introduction, Fault Types and Models, Controllability and Observability, Ad Hoc Testable Design Techniques, Scan Based and BIST Techniques<\/p>\n

Course Objectives:<\/h4>\n
    \n
  1. To learn basic CMOS Circuits.<\/li>\n
  2. To learn CMOS process technology.<\/li>\n
  3. To learn techniques of chip design using programmable devices.<\/li>\n
  4. To learn the concepts of designing VLSI Subsystems.<\/li>\n
  5. To learn the concepts of modelling a digital system using Hardware Description Language.<\/li>\n<\/ol>\n

    Course Outcomes:<\/h4>\n