7th Sem, ECE

Vlsi Design ECE 7th Sem Syllabus for AKTU B.Tech 2019-20 Scheme

Vlsi Design detail syllabus for Electronics & Communication Engineering (Ece), 2019-20 scheme is taken from AKTU official website and presented for AKTU students. The course code (REC702), and for exam duration, Teaching Hr/Week, Practical Hr/Week, Total Marks, internal marks, theory marks, duration, and credits do visit complete sem subjects post given below.

For all other ece 7th sem syllabus for b.tech 2019-20 scheme aktu you can visit ECE 7th Sem syllabus for B.Tech 2019-20 Scheme AKTU Subjects. The detail syllabus for vlsi design is as follows.

Unit I

For the complete syllabus, results, class timetable and more kindly download iStudy. It’s a lightweight, easy to use, no images, no pdfs platform to make student’s life easier.

Unit II

Delay: Introduction, Transient Response, RC delay model, Linear Delay Model, Logical Effort of Paths, Timing Analysis Delay Models. Power: Introduction, Dynamic Power, Static Power

Unit III

Energy-Delay Optimization, Low Power Architectures. Interconnect: Introduction, Interconnect Modelling, Interconnect Impact, Interconnect Engineering, Logical Effort with Wires

Unit IV

For the complete syllabus, results, class timetable and more kindly download iStudy. It’s a lightweight, easy to use, no images, no pdfs platform to make student’s life easier.

Unit V

Low-Power CMOS Logic Circuits: Introduction, Overview of Power Consumption, Low-Power Design through voltage scaling, Estimation and Optimization of switching activity, Reduction of Switched Capacitance and Adiabatic Logic Circuits. Design for Testability: Introduction, Fault Types and Models, Controllability and Observability, Ad Hoc Testable Design Techniques, Scan Based and BIST Techniques

Course Objectives:

  1. To learn basic CMOS Circuits.
  2. To learn CMOS process technology.
  3. To learn techniques of chip design using programmable devices.
  4. To learn the concepts of designing VLSI Subsystems.
  5. To learn the concepts of modelling a digital system using Hardware Description Language.

Course Outcomes:

  • Model the behaviour of a MOS Transistor.
  • Design combinational and sequential circuits using CMOS gates.
  • Identify the sources of power dissipation in a CMOS circuit.
  • Analyse SRAM cell and memory arrays.

Reference Books:

  1. D. A. Pucknell and K. Eshraghian, Basic VLSI Design: Systems and Circuits, PHI, 3rd Ed.,1994.
  2. W.Wolf, Modern VLSI Design: System on Chip, Third Edition, Pearson, 2002.
  3. Sung-Mo Kang & Yosuf Leblebici, CMOS Digital Integrated Circuits: Analysis & Design,Mcgraw Hill, 4th Edition.
  4. Neil H.E.Weste, David Money Harris, CMOS VLSI Design-A circuits and SystemsPerspective Pearson, 4th Edition

For detail syllabus of all other subjects of B.Tech Ece, 2019-20 scheme do visit Ece 7th Sem syllabus for 2019-20 scheme.

Don’t forget to download iStudy for the latest syllabus, results, class timetable and more.

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