VLSI Design Lab detail syllabus for Electronics & Telecommunication Engineering (ETE), 2021-22 scheme is taken from AKTUs official website and presented for the AKTU B.Tech students. For the course code (KEC753B), exam duration, teaching hr/week, practical hr/week, total marks, internal marks, theory marks, duration, credits, and other details do visit complete semester subjects post given below.
For the ETE 7th Sem Syllabus for AKTU B.Tech 2021-22 Scheme you can visit ETE 7th Sem 2021-22 Scheme. For the Departmental Elective Lab-I scheme of ETE 7th Sem 2021-22 regulation do refer to Departmental Elective Lab-I ETE 7th Sem scheme. The detail syllabus for vlsi design lab is as follows.
List of Experiments:
- Design and analysis of basic of logic Gates: AND, OR, NOT, NAND, NOR, XOR, XNOR.
- Design and implementation of Half adder and Full adder using CMOS logic.
- To simulate the schematic of the common drain amplifier.
- To simulate the schematic of the differential amplifier.
- To simulate the schematic of the operational amplifier.
- Design of 3-8 decoder using MOS technology.
- Design a 4:1 Multiplexer.
- Design and implementation of Flip flop circuit.
- Layout design of PMOS, NMOS transistors.
- Layout design of CMOS inverter and its analysis.
Course Outcomes:
At the end of this course students will demonstrate the ability to:
- Designing of logic gates.
- Implementation of combinational and sequential circuits using CMOS logic.
- Analyze amplifier circuits.
- Design sequential circuits such as flip flop.
- Do the layout designing for physical analysis of the MOS transistor and MOS based circuits.
For the syllabus of all the subjects of B.Tech ETE 7th Sem, 2021-22 scheme do visit ETE 7th Sem syllabus subjects.
For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.