{"id":3743,"date":"2022-01-22T07:06:42","date_gmt":"2022-01-22T07:06:42","guid":{"rendered":"https:\/\/www.inspirenignite.com\/rj\/7ec4-21-vlsi-design-lab-syllabus-for-ece-7th-sem-2020-21-regulation-rtu\/"},"modified":"2022-01-22T07:06:42","modified_gmt":"2022-01-22T07:06:42","slug":"7ec4-21-vlsi-design-lab-syllabus-for-ece-7th-sem-2020-21-regulation-rtu","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/rj\/7ec4-21-vlsi-design-lab-syllabus-for-ece-7th-sem-2020-21-regulation-rtu\/","title":{"rendered":"7EC4-21: VLSI Design Lab Syllabus for ECE 7th Sem 2020-21 Regulation RTU"},"content":{"rendered":"

VLSI Design Lab detailed syllabus for Electronics & Communication Engineering (ECE) for 2020-21 regulation curriculum has been taken from the Rajasthan Technical University<\/a> official website and presented for the electronics & communication engineering students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below. <\/p>\n

For Electronics & Communication Engineering 7th Sem scheme and its subjects, do visit ECE 7th Sem 2020-21 regulation scheme<\/a>. The detailed syllabus of vlsi design lab is as follows. <\/p>\n

VLSI Design Lab<\/title><\/p>\n<h4>Part-A<\/h4>\n<p> Step 1 Write the VHDL\/Verilog code using VHDL software for following experiment and simulate them. Step 2. Burn the Written code in Xilling Board and test the output with real input signal<\/p>\n<ol>\n<li>Design and simulate all the logic gates with 2 inputs using VHDL\/Verilog.<\/li>\n<li>Design and simulate 2-to-4 decoder,3-to-8 encoder and 8X1 multiplexer using VHDL\/Verilog.<\/li>\n<li>Design and simulate half adder and full adder using VHDL (data flow method)\/Verilog.<\/li>\n<li>Design and simulate D, T and J-K flip flop using VHDL\/Verilog.<\/li>\n<li>Design a 4bit binary Asynchronous and synchronous counter. Obtain its number of gates, area, and speed and power dissipation.<\/li>\n<li>Design a 4- bit Serial in-serial out shift register. Obtain its number of gates, area, and speed and power dissipation.<\/li>\n<\/ol>\n<h4>Part-B<\/h4>\n<p> Step-1 Design and simulate following experiment using ECAD software Viz. Mentor graphics, Orcade Pspice, Cadence etc. Step-2 Draw the layout (without any DRC error)of the schematic obtain in step 1 and obtain post layout simulation using appropriate ECAD software.<\/p>\n<ol>\n<li>Design and simulate all the logic gates (NOT, NAND and NOR) with 2 inputs in CMOS Technology.<\/li>\n<li>Design and simulate Y = AB (C+D), Y = A+B(C+D) and 4X1 multiplexer using CMOS Technology.<\/li>\n<li>Design and simulate half adder and full adder using CMOS Technology.<\/li>\n<li>Design and simulate SR flip flop using CMOS Technology.<\/li>\n<li>Design and Simulate any DRAM cell.<\/li>\n<\/ol>\n<p align=\"justify\">For detailed syllabus of all other subjects of Electronics & Communication Engineering, 2020-21 regulation curriculum do visit <a class=\"rank-math-link\" href=\"..\/category\/ece+7th-sem\">ECE 7th Sem subject syllabuses for 2020-21 regulation<\/a>. <\/p>\n<p align=\"justify\">For all Electronics & Communication Engineering results, visit <a class=\"rank-math-link\" href=\"https:\/\/www.inspirenignite.com\/rj\/category\/results\/\">Rajasthan Technical University electronics & communication engineering all semester results<\/a> direct link. <\/p>\n","protected":false},"excerpt":{"rendered":"<p>VLSI Design Lab detailed syllabus for Electronics & Communication Engineering (ECE) for 2020-21 regulation curriculum has been taken from the Rajasthan Technical University official website and presented for the electronics […]<\/p>\n","protected":false},"author":2491,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[11,26],"tags":[],"class_list":["post-3743","post","type-post","status-publish","format-standard","hentry","category-7th-sem","category-ece"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/rj\/wp-json\/wp\/v2\/posts\/3743","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/rj\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/rj\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/rj\/wp-json\/wp\/v2\/users\/2491"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/rj\/wp-json\/wp\/v2\/comments?post=3743"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/rj\/wp-json\/wp\/v2\/posts\/3743\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/rj\/wp-json\/wp\/v2\/media?parent=3743"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/rj\/wp-json\/wp\/v2\/categories?post=3743"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/rj\/wp-json\/wp\/v2\/tags?post=3743"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}