{"id":19519,"date":"2020-09-13T07:50:47","date_gmt":"2020-09-13T07:50:47","guid":{"rendered":"https:\/\/www.inspirenignite.com\/mh\/btetoe605a-digital-system-design-syllabus-for-et-6th-sem-2019-20-dbatu-open-elective-i\/"},"modified":"2020-09-13T07:50:47","modified_gmt":"2020-09-13T07:50:47","slug":"btetoe605a-digital-system-design-syllabus-for-et-6th-sem-2019-20-dbatu-open-elective-i","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/mh\/btetoe605a-digital-system-design-syllabus-for-et-6th-sem-2019-20-dbatu-open-elective-i\/","title":{"rendered":"BTETOE605A: Digital System Design Syllabus for ET 6th Sem 2019-20 DBATU (Open Elective-I)"},"content":{"rendered":"

Digital System Design detailed syllabus scheme for Electronics & Telecommunication Engineering (ET), 2019-20 onwards has been taken from the DBATU<\/a> official website and presented for the Bachelor of Technology students. For Subject Code, Course Title, Lecutres, Tutorials, Practice, Credits, and other information, do visit full semester subjects post given below. <\/p>\n

For 6th Sem Scheme of Electronics & Telecommunication Engineering (ET), 2019-20 Onwards, do visit ET 6th Sem Scheme, 2019-20 Onwards<\/a>. For the Open Elective-I scheme of 6th Sem 2019-20 onwards, refer to ET 6th Sem Open Elective-I Scheme 2019-20 Onwards<\/a>. The detail syllabus for digital system design is as follows.<\/p>\n

Digital System Design Syllabus for Electronics & Telecommunication Engineering (ET) 3rd Year 6th Sem 2019-20 DBATU<\/h2>\n

Digital System Design<\/title><\/p>\n<h4>Course Objectives:<\/h4>\n<p id=\"istudy\" style=\"text-align:center\">For the complete syllabus, results, class timetable, and many other features kindly download the <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">iStudy App<\/a><br \/><b> It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.<\/b><br \/><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px\"><\/a>. <\/p>\n<h4>Course Outcomes:<\/h4>\n<p> At the end of this course students will demonstrate the ability to<\/p>\n<ol>\n<li>Design and analyze combinational logic circuits<\/li>\n<li>Design & analyze modular combinational circuits with MUX\/DEMUX, Decoder, Encoder<\/li>\n<li>Design & analyze synchronous sequential logic circuits<\/li>\n<li>Use HDL & appropriate EDA tools for digital logic design and simulation.<\/li>\n<\/ol>\n<h4>UNIT – 1<\/h4>\n<p> Logic Simplification and Combinational Logic Design Review of Boolean algebra and De Morgans Theorem, SOP & POS forms, Canonical forms, Karnaugh maps up to 6 variables, Binary codes, Code Conversion.<\/p>\n<h4>UNIT – 2<\/h4>\n<p id=\"istudy\" style=\"text-align:center\">For the complete syllabus, results, class timetable, and many other features kindly download the <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">iStudy App<\/a><br \/><b> It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.<\/b><br \/><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px\"><\/a>. <\/p>\n<h4>UNIT – 3<\/h4>\n<p> Sequential Logic Design Building blocks like S-R, JK and Master-Slave JK FF, Edge triggered FF, Ripple and Synchronous counters, Shift registers, Finite state machines, Design of synchronous FSM, Algorithmic State Machines charts. Designing synchronous circuits like Pulse train generator, Pseudo Random Binary Sequence generator, Clock generation<\/p>\n<h4>UNIT – 4<\/h4>\n<p> Logic Families and Semiconductor Memories TTL NAND gate, Specifications, Noise margin, Propagation delay, fan-in, fan-out, Tristate TTL, ECL, CMOS families and their interfacing.<\/p>\n<h4>UNIT – 5<\/h4>\n<p id=\"istudy\" style=\"text-align:center\">For the complete syllabus, results, class timetable, and many other features kindly download the <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">iStudy App<\/a><br \/><b> It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.<\/b><br \/><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px\"><\/a>. <\/p>\n<h4>UNIT – 6<\/h4>\n<p> VLSI Design flow Design entry: Schematic, FSM & HDL, different modeling styles in VHDL, Data types and objects, Dataflow, Behavioral and Structural Modeling, Synthesis and Simulation VHDL constructs and codes for combinational and sequential circuits.<\/p>\n<h4>Text Books:<\/h4>\n<ol>\n<li>R.P. Jain, Modern digital Electronics, Tata McGraw Hill, 4th edition, 2009.<\/li>\n<li>Douglas Perry, VHDL, Tata McGraw Hill, 4th edition, 2002.<\/li>\n<li>W.H. Gothmann, Digital Electronics- An introduction to theory and practice, PHI, 2nd edition, 2006.<\/li>\n<li>D.V. Hall, Digital Circuits and Systems , Tata McGraw Hill, 1989<\/li>\n<li>Charles Roth, Digital System Design using VHDL, Tata McGraw Hill 2nd edition 2012.<\/li>\n<\/ol>\n<p align=\"justify\">For detail syllabus of all subjects of Electronics & Telecommunication Engineering (ET) 6th Sem 2019-20 onwards, visit <a href=\"..\/category\/dbatu\/6th-sem-dbatu\">ET 6th Sem Subjects <\/a>of 2019-20 Onwards.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Digital System Design detailed syllabus scheme for Electronics & Telecommunication Engineering (ET), 2019-20 onwards has been taken from the DBATU official website and presented for the Bachelor of Technology students. […]<\/p>\n","protected":false},"author":2351,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[108],"tags":[],"class_list":["post-19519","post","type-post","status-publish","format-standard","hentry","category-et-dbatu"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/posts\/19519","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/users\/2351"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/comments?post=19519"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/posts\/19519\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/media?parent=19519"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/categories?post=19519"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/tags?post=19519"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}