{"id":19462,"date":"2020-09-13T07:50:20","date_gmt":"2020-09-13T07:50:20","guid":{"rendered":"https:\/\/www.inspirenignite.com\/mh\/btetpe703c-vlsi-design-technology-syllabus-for-et-7th-sem-2020-21-dbatu-elective-iv-labs\/"},"modified":"2020-09-13T07:50:20","modified_gmt":"2020-09-13T07:50:20","slug":"btetpe703c-vlsi-design-technology-syllabus-for-et-7th-sem-2020-21-dbatu-elective-iv-labs","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/mh\/btetpe703c-vlsi-design-technology-syllabus-for-et-7th-sem-2020-21-dbatu-elective-iv-labs\/","title":{"rendered":"BTETPE703C: Vlsi Design & Technology Syllabus for ET 7th Sem 2020-21 DBATU (Elective-IV Labs)"},"content":{"rendered":"

Vlsi Design & Technology detailed syllabus scheme for Electronics & Telecommunication Engineering (ET), 2020-21 onwards has been taken from the DBATU<\/a> official website and presented for the Bachelor of Technology students. For Subject Code, Course Title, Lecutres, Tutorials, Practice, Credits, and other information, do visit full semester subjects post given below. <\/p>\n

For 7th Sem Scheme of Electronics & Telecommunication Engineering (ET), 2020-21 Onwards, do visit ET 7th Sem Scheme, 2020-21 Onwards<\/a>. For the Elective-IV Labs scheme of 7th Sem 2020-21 onwards, refer to ET 7th Sem Elective-IV Labs Scheme 2020-21 Onwards<\/a>. The detail syllabus for vlsi design & technology is as follows.<\/p>\n

Vlsi Design & Technology Syllabus for Electronics & Telecommunication Engineering (ET) 4th Year 7th Sem 2020-21 DBATU<\/h2>\n

VLSI Design & Technology<\/title><\/p>\n<h4>Course Objectives:<\/h4>\n<p id=\"istudy\" style=\"text-align:center\">For the complete syllabus, results, class timetable, and many other features kindly download the <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">iStudy App<\/a><br \/><b> It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.<\/b><br \/><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px\"><\/a>. <\/p>\n<h4>Course Outcomes:<\/h4>\n<p> After successfully completing the course, students will be able to<\/p>\n<ol>\n<li>Model digital circuit with HDL, simulate, synthesis and prototype in PLDs.<\/li>\n<li>Understand chip level issues and need of testability.<\/li>\n<li>Design analog & digital CMOS circuits for specified applications<\/li>\n<\/ol>\n<h4>UNIT – 1<\/h4>\n<p> VHDL Modeling Data objects, Data types, Entity, Architecture & types of modeling, Sequential statements, Concurrent statements, Packages, Sub programs, Attributes, VHDL Test bench, Test benches using text files. VHDL modeling of Combinational, Sequential logics & FSM, Meta-stability.<\/p>\n<h4>UNIT – 2<\/h4>\n<p id=\"istudy\" style=\"text-align:center\">For the complete syllabus, results, class timetable, and many other features kindly download the <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">iStudy App<\/a><br \/><b> It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.<\/b><br \/><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px\"><\/a>. <\/p>\n<h4>UNIT – 3<\/h4>\n<p> SoC & Interconnect Clock skew, Clock distribution techniques, clock jitter, Supply and ground bounce, power distribution techniques. Power optimization, Interconnect routing techniques; wire parasitic, Signal integrity issues, I\/O architecture, pad design, Architectures for low power.<\/p>\n<h4>UNIT – 4<\/h4>\n<p> Digital CMOS Circuits MOS Capacitor, MOS Transistor theory, C-V characteristics, Non ideal I-V effects, Technology Scaling. CMOS inverters, DC transfer characteristics, Power components, Power delay product, Transmission gate. CMOS combo logic design, Delays: RC delay model, Effective resistance, Gate and diffusion capacitance, Equivalent RC circuits; Linear delay model, Logical effort, Parasitic delay, Delay in a logic gate, Path logical efforts.<\/p>\n<h4>UNIT -5<\/h4>\n<p id=\"istudy\" style=\"text-align:center\">For the complete syllabus, results, class timetable, and many other features kindly download the <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">iStudy App<\/a><br \/><b> It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.<\/b><br \/><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px\"><\/a>. <\/p>\n<h4>UNIT – 6<\/h4>\n<p> Testability Types of fault, Need of Design for Testability (DFT), Testability, Fault models, Path sensitizing, Sequential circuit test, BIST, Test pattern generation, JTAG & Boundary scan, TAP Controller.<\/p>\n<h4>Text Books:<\/h4>\n<ol>\n<li>Charles H. Roth, Digital systems design using VHDL, PWS.<\/li>\n<li>Wyane Wolf, Modern VLSI Design (System on Chip), PHI Publication.<\/li>\n<li>Allen Holberg, Analog CMOS Design, Oxford University Press.<\/li>\n<li>Neil H. E. Weste, David Money Harris, CMOS VLSI Design: A Circuit & System Perspective, Pearson Publication.<\/li>\n<\/ol>\n<p align=\"justify\">For detail syllabus of all subjects of Electronics & Telecommunication Engineering (ET) 7th Sem 2020-21 onwards, visit <a href=\"..\/category\/dbatu\/7th-sem-dbatu\">ET 7th Sem Subjects <\/a>of 2020-21 Onwards.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Vlsi Design & Technology detailed syllabus scheme for Electronics & Telecommunication Engineering (ET), 2020-21 onwards has been taken from the DBATU official website and presented for the Bachelor of Technology […]<\/p>\n","protected":false},"author":2351,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[108],"tags":[],"class_list":["post-19462","post","type-post","status-publish","format-standard","hentry","category-et-dbatu"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/posts\/19462","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/users\/2351"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/comments?post=19462"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/posts\/19462\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/media?parent=19462"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/categories?post=19462"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/mh\/wp-json\/wp\/v2\/tags?post=19462"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}