ITL301: Digital Design Lab Syllabus for IT 3rd Sem 2017 Pattern Mumbai University

Digital Design Lab detailed syllabus scheme for Information Technology (IT), 2017 regulation has been taken from the University of Mumbai official website and presented for the Bachelor of Engineering students. For Course Code, Course Title, Test 1, Test 2, Avg, End Sem Exam, Team Work, Practical, Oral, Total, and other information, do visit full semester subjects post given below.

For all other Mumbai University Information Technology 3rd Sem Syllabus 2017 Pattern, do visit IT 3rd Sem 2017 Pattern Scheme. The detailed syllabus scheme for digital design lab is as follows.

Digital Design Lab Syllabus for Information Technology SE 3rd Sem 2017 Pattern Mumbai University

Lab Objectives:

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Lab Outcomes:

Students will be able to:

1. Minimize the Boolean algebra and design it using logic gates.
2. Analyse and design combinational circuit.
3. Realise given function using combinational circuit.
4. Design and develop sequential circuits
5. Implement digital systems using programmable logic devices
6. Translate real world problems into digital logic formulations using VHDL.

Prerequisites:

Concepts of Logic Design

Hardware requirement:

Digital Trainer kit, ICs for various logic gates and functions, connecting wires

Software requirement:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
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Module I

Boolean Algebra and Logic gates

1. Verify the truth table of logic gates (basic and universal gates)
2. Realization of Boolean algebra using gates 04 LO1

Module II

Design and Analysis of Combinational Circuits

1. Design of Full Adder and Full Subtractor.
2. verify the operation of 4- bit magnitude comparator 04 LO2

Module III

Implementation of Combinational Circuits

1. Implementation of MUX and DeMUX.
2. Implementation of Encoder and Decoder 04 LO3

Module IV

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
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Module V

Programmable logic Devices

1. Evaluate and observe Boolean expression using PALs and PLAs. 04 LO5

Module VI

VHDL

1. Implementation of Logic Gates using VHD
2. Evaluate and observe combinational circuits on VHDL. 04 LO6

Text Books:

1. R. P. Jain, Modern Digital Electronics, Tata McGraw Hill.
2. Balbaniam,Carison,Digital Logic Design Principles, Wiley Publication

Reference Books:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
.

Term Work:

Term Work shall consist of at least 10 to 12 practicals based on the above list. Also Term work Journal must include at least 2 assignments. Term Work Marks: 25 Marks (Total marks) = 15 Marks (Experiment) + 5 Marks (Assignments) + 5 Marks (Attendance) Oral& Practical Exam: An Oral & Practical exam will be held based on the above syllabus.

For detail syllabus of all other subjects of Information Technology (IT) 3rd Sem 2017 regulation, visit IT 3rd Sem Subjects syllabus for 2017 regulation.