ITC302: Logic Design Syllabus for IT 3rd Sem 2017 Pattern Mumbai University

Logic Design detailed syllabus scheme for Information Technology (IT), 2017 regulation has been taken from the University of Mumbai official website and presented for the Bachelor of Engineering students. For Course Code, Course Title, Test 1, Test 2, Avg, End Sem Exam, Team Work, Practical, Oral, Total, and other information, do visit full semester subjects post given below.

For all other Mumbai University Information Technology 3rd Sem Syllabus 2017 Pattern, do visit IT 3rd Sem 2017 Pattern Scheme. The detailed syllabus scheme for logic design is as follows.

Logic Design Syllabus for Information Technology SE 3rd Sem 2017 Pattern Mumbai University

Course Objectives:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
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Course Outcomes:

Students will able to:

1. Understand the concepts of various components to design stable analog circuits.
2. Represent numbers and perform arithmetic operations.
3. Minimize the Boolean expression using Boolean algebra and design it using logic gates
4. Analyze and design combinational circuit.
5. Design and develop sequential circuits
6. Translate real world problems into digital logic formulations using VHDL.

Prerequisites:

Basic Electrical Engineering

Module I

Biasing of BJT Biasing of BJT: DC operating point, BJT characteristics & parameters, all biasing circuits, analysis of above circuits and their design, variation of operation point and its stability. Differential 08 CO1 Amplifier, constant current source, current mirror.

Module II

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Module III

Boolean Algebra and Logic gates Introduction, NAND and NOR operations, Exclusive -OR and Exclusive -NOR operations, Boolean Algebra Theorems and Properties , Standard SOP and POS form, Reduction of Boolean functions using Algebric method, K -map method (2,3,4 Variable).Variable entered Maps, Quine Mc Cluskey, Mixed Logic Combinational Circuits and multiple output function Basic Digital Circuits: NOT,AND, OR,NAND,NOR,EX-OR,EX-NOR Gates. 10 CO2 CO3

Module IV

Design and Analysis of Combinational Circuits Introduction, Half and Full Adder, Half and Full Subtractor, Four Bit Binary Adder, One digit BCD Adder, code conversion, Encoder and Decoder ,Multiplexers and Demultiplexers, Decoders, Binary comparator (2,3 variable)4-bit Magnitude Comparator IC 7485 and ALU IC74181. 08 CO2 CO3 CO4

Module V

Sequential Logic Design Flip Flops : SR, JK, D, T, master slave flip flop, Truth Table, excitation table and conversion Register: Shift register, SISO, SIPO, PISO, PIPO, Bi-directional and universal shift register. Counters: Design of synchronous and asynchronous ,Modulo Counter, Up Down counter IC 74193, Ring and Johnson Counter 9 CO4 CO5

Module VI

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
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Text Books:

1. Robert L. Boylestad, Louis Nashelsky, Electronic devices and circuit Theory, PHI
2. R. P. Jain, Modern Digital Electronics, Tata McGraw Hill.
3. M. Morris Mano, Digital Logic and computer Design, PHI
4. J. Bhasker. VHDL Primer, Pearson Education.
5. Balbaniam,Carison,Digital Logic Design Principles, Wiley Publication

Reference Books:

1. Martin
   1. Roden, Gordon L. Carpenter, William R. Wieserman Electronic Design-From Concept to Reality, Shroff Publishers and Distributors.
2. A. Anand Kumar, Fundamentals of Digital Circuits , Prentice Hall India
3. Subrata Ghosal, Digital Electronics, Cengage Learning.
4. Anil K. Maini, Digital Electronics Principles and Integrated Circuits, Wiley India
5. Donald p Leach, Albert Paul Malvino, Digital principles and Applications, Tata McGraw Hill

Assessment:

Internal Assessment for 20 marks: Consisting of Two Compulsory Class Tests Approximately 40% to 50% of syllabus content must be covered in First test and remaining 40% to 50% of syllabus contents must be covered in second test. End Semester Theory Examination: Some guidelines for setting the question papers are as:

• Weightage of each module in end semester examination is expected to be/will be proportional to number of respective lecture hours mentioned in the syllabus.
• Question paper will comprise of total six questions, each carrying 20 marks.
• Q.1 will be compulsory and should cover maximum contents of the syllabus.
• Remaining question will be mixed in nature (for example if Q.2 has part
1. from module 3 then part
2. will be from any other module. (Randomly selected from all the modules)
• Total four questions need to be solved.

For detail syllabus of all other subjects of Information Technology (IT) 3rd Sem 2017 regulation, visit IT 3rd Sem Subjects syllabus for 2017 regulation.