4th Sem, Electronics Engg

ELXL403: Digital System Design Laboratory Syllabus for EL 4th Sem 2016 Pattern Mumbai University

Digital System Design Laboratory detailed syllabus scheme for Electronics Engineering (EL), 2016 regulation has been taken from the University of Mumbai official website and presented for the Bachelor of Engineering students. For Course Code, Course Title, Test 1, Test 2, Avg, End Sem Exam, Team Work, Practical, Oral, Total, and other information, do visit full semester subjects post given below.

For all other Mumbai University Electronics Engineering 4th Sem Syllabus 2016 Pattern, do visit EL 4th Sem 2016 Pattern Scheme. The detailed syllabus scheme for digital system design laboratory is as follows.

Digital System Design Laboratory Syllabus for Electronics Engineering SE 4th Sem 2016 Pattern Mumbai University

Digital System Design Laboratory

Term Work:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
Get it on Google Play.

Suggested List of Experiments

However Instructor is free to design own experiments as per the guidelines Experiments based on Hardware:

  1. Implementation of Counter using IC 7490, IC 7493
  2. Implementation of Synchronous Counter using MSI counter ICs
  3. Implementation of Universal Shift Register using IC 74194
  4. Design and implement Moore Machine
  5. Design and implement Mealy Machine
  6. Serial Adder using a Melay/Moore Machine.
  7. Design Sequence Detector using FF

Suggested experiments based on software:

  1. Implement basic digital logic gates and simulate with HDL.
  2. Implement basic Flip Flops and simulate with HDL.
  3. Design and implement full adder logic with HDL and simulate the same.
  4. Design and implement multiplexer with HDL and simulate the same.
  5. Design and implement multiplexer with HDL and simulate the same.
  6. Design and implement decoder (74138) with HDL and simulate the same.
  7. Design and implement 4-bit counter with HDL and simulate the same.
  8. Design and implement shift register with HDL and simulate the same.
  9. Design and simulate the Finite State Machine (FSM) design by HDL.
  10. Design and simulate the ALU design by HDL.

Additional suggested experiments (optional) Implementation of any of above using CPLD/FPGA

For detail syllabus of all other subjects of Electronics Engineering (EL) 4th Sem 2016 regulation, visit EL 4th Sem Subjects syllabus for 2016 regulation.

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