EC 42 B: Vlsi Design Syllabus for ET 7th Sem 2017 DBATU (Elective-IX)

Vlsi Design detailed syllabus scheme for Electronics & Telecommunication Engineering (ET), 2017 onwards has been taken from the DBATU official website and presented for the Bachelor of Technology students. For Subject Code, Course Title, Lecutres, Tutorials, Practice, Credits, and other information, do visit full semester subjects post given below.

For 7th Sem Scheme of Electronics & Telecommunication Engineering (ET), 2017 Onwards, do visit ET 7th Sem Scheme, 2017 Onwards. For the Elective-IX scheme of 7th Sem 2017 onwards, refer to ET 7th Sem Elective-IX Scheme 2017 Onwards. The detail syllabus for vlsi design is as follows.

Vlsi Design Syllabus for Electronics & Telecommunication Engineering (ET) 4th Year 7th Sem 2017 DBATU

Course Objectives:

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
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Course Outcomes:

1. Model digital circuit with HDL, simulate, synthesis and prototype in PLDs.
2. Understand chip level issues and need of testability.
3. Design analog and digital CMOS circuits for specified applications.

Unit 1

VHDL Modeling
Data objects, Data types, Entity, Architecture and types of modeling, Sequential statements, Concurrent statements, Packages, Sub programs, Attributes, VHDL Test bench, Test benches using text files. VHDL modeling of Combinational, Sequential logics and FSM, Meta-stability.

Unit 2

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
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Unit 3

SoC and Interconnect
Clock skew, Clock distribution techniques, clock jitter. Supply and ground bounce, power distribution techniques. Power optimization. Interconnect routing techniques; wire parasitic, Signal integrity issues. I/O architecture, pad design, Architectures for low power.

Unit 4

Digital CMOS Circuits
MOS Capacitor, MOS Transistor theory, C-V characteristics, Non ideal I-V effects, Technology Scaling. CMOS inverters, DC transfer characteristics, Power components, Power delay product. Transmission gate. CMOS combo logic design. Delays: RC delay model, Effective resistance, Gate and diffusion capacitance, Equivalent RC circuits; Linear delay model, Logical effort, Parasitic delay, Delay in a logic gate, Path logical efforts.

Unit 5

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
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Unit 6

Testability
Types of fault, Need of Design for Testability (DFT), Testability, Fault models, Path sensitizing, Sequential circuit test, BIST, Test pattern generation, JTAG and Boundary scan, TAP Controller.

Reference/Text Book:

1. Charles H. Roth, Digital systems design using VHDL, PWS.
2. Wyane Wolf, Modern VLSI Design (System on Chip), PHI Publication.
3. Allen Holberg, Analog CMOS Design, Oxford University Press.
4. Neil H. E. Weste, David Money Harris, CMOS VLSI Design: A Circuit and System Perspective, Pearson Publication.

For detail syllabus of all subjects of Electronics & Telecommunication Engineering (ET) 7th Sem 2017 onwards, visit ET 7th Sem Subjects of 2017 Onwards.