ECL302: Digital System Design Laboratory Syllabus for EC 3rd Sem 2017 Pattern Mumbai University

Digital System Design Laboratory detailed syllabus scheme for Electronics & Telecommunication Engineering (EC), 2017 regulation has been taken from the University of Mumbai official website and presented for the Bachelor of Engineering students. For Course Code, Course Title, Test 1, Test 2, Avg, End Sem Exam, Team Work, Practical, Oral, Total, and other information, do visit full semester subjects post given below.

For all other Mumbai University Electronics & Telecommunication Engineering 3rd Sem Syllabus 2017 Pattern, do visit EC 3rd Sem 2017 Pattern Scheme. The detailed syllabus scheme for digital system design laboratory is as follows.

Digital System Design Laboratory Syllabus for Electronics & Telecommunication Engineering SE 3rd Sem 2017 Pattern Mumbai University

Laboratory plan

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Suggested list of experiments:

1. Verify different logic gates.
2. Simplification of Boolean functions.
3. Verify Universal gates NAND and NOR and design EXOR and EXNOR gates using Universal gates.
4. Implement Half adder, Full adder, Half subtractor and Full subtractor circuits.
5. Implement BCD adder using four bit binary adder IC-7483.
6. Flip flops conversion JK to D, JK to T and D to TFF.
7. Implement logic equations using Multiplexer.
8. Design synchronous MOD N counter using IC-7490.
9. Verify encoder and decoder operations.
10. Implement digital circuits to perform binary to gray and gray to binary operations.
11. Verify truth table of different types of flip flops.
12. Verify different counter operations.
13. Write VHDL simulation code for different logic gates.
14. Write VHDL simulation code for combinational and sequential circuits
15. Write VHDL simulation code for 4:1 Multiplexer, 2 line to 4 line binary decoder

Minimum One project Suggested list of Mini Projects:

1. Design Clock pulse generator.
2. Design Clap operated remote control for Fan.
3. Design BCD counter and show operation on Seven Segment Display.
4. Design digital stop watch.
5. Write VHDL code to implement traffic light controller.
6. Design water level indicator for overhead water tank.
7. Design frequency divider circuit.
8. Design switch debounce circuit.
9. Design sequence generator circuit.
10. Design sequence detector circuit.
11. Design Even/Odd parity generator/checker circuit.
12. Design simple LED flasher circuit.
13. Design digital dice.
14. Design fastest finger first indicator.
15. Design Toggle switch using TFF.

Note: Small project should be considered as a part of term-work.

Term Work: At least 08 Experiments including 02 simulations covering entire syllabus must be given during the Laboratory session batch wise. Computation/simulation based experiments are also encouraged. The experiments should be students centric and attempt should be made to make experiments more meaningful, interesting and innovative. Application oriented one mini-project can be conducted for maximum batch of four students. Term work assessment must be based on the overall performance of the student with every experiments/tutorials and mini-projects are graded from time to time. The grades will be converted to marks as per Choice Based Credit and Grading System manual and should be added and averaged. Based on above scheme grading and term work assessment should be done. The practical and oral examination will be based on entire syllabus.

For detail syllabus of all other subjects of Electronics & Telecommunication Engineering (EC) 3rd Sem 2017 regulation, visit EC 3rd Sem Subjects syllabus for 2017 regulation.