ECCDLO5013: Finite Automata Theory Syllabus for EC 5th Sem 2018 Pattern Mumbai University (Department Level Optional Course-1)

Finite Automata Theory detailed syllabus scheme for Electronics & Telecommunication Engineering (EC), 2018 regulation has been taken from the MU official website and presented for the Bachelor of Engineering students. For Course Code, Course Title, Test 1, Test 2, Avg, End Sem Exam, Team Work, Practical, Oral, Total, and other information, do visit full semester subjects post given below.

For 5th Sem Scheme of Electronics & Telecommunication Engineering (EC), 2018 Pattern, do visit EC 5th Sem Scheme, 2018 Pattern. For the Department Level Optional Course-1 scheme of 5th Sem 2018 regulation, refer to EC 5th Sem Department Level Optional Course-1 Scheme 2018 Pattern. The detail syllabus for finite automata theory is as follows.

Finite Automata Theory Syllabus for Electronics & Telecommunication Engineering TE 5th Sem 2018 Pattern Mumbai University

Course Objectives:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
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Course Outcomes:

After successful completion of the course student will be able to

• Manipulate simple Boolean expressions using the theorems and postulates of Boolean algebra and to minimize combinational functions.
• Design and analyze small combinational circuits and to use standard combinational functions/ building blocks to build larger more complex circuits.
• Design and analyze small sequential circuits and devices and to use standard sequential functions/ building blocks to build larger more complex circuits.
• Design finite state machine understand the fundamentals and areas of applications for the integrated circuits.
• Perform symmetric and cascade threshold function and element

Module 1

Combinational Logic 09

1. Notations of sets, Relations and Lattices, Venn diagram
2. Switching Algebra and functions, Boolean algebras and functions, Minimization of Boolean functions using map method and Tabulation Method, Prime implicant chart, Reduction of the chart, Branching method
3. Design of combinational Logic circuits, Contact networks, Functional decomposition and symmetric functions. Identification of symmetric functions

Module 2

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It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
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Module 3

Testing of Combinational Circuits 09

1. Reliable Design and fault Diagnosis, Fault Detection in combinational circuits, Fault location experiments, Fault Detection by Boolean Differences and path sensitization, Synthesis for testability, Multiple fault detection using map method, failure-Tolerant Design.

Module 4

Sequential Circuits 12

1. Synchronous sequential circuits and iterative networks: Memory elements and their excitation functions; Synthesis of synchronous sequential circuits, Capabilities and limitations, State equivalence and Minimization, Minimization of completely specified and Incompletely specified sequential machines, Partition technique, Merger methods
2. Asynchronous sequential circuits: Hazards, Synthesis, State assignment and minimization
3. Finite state Machines – Mealy and Moore synchronous and asynchronous sequential circuits Design,

Module 5

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
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Module 6

Algorithmic State Machine 04

1. Introduction and components of ASM charts, Representation of sequential circuits using ASM charts, Example using ASM chart: 2 bit counter, binary multiplier, Weighing machine etc.

Text Books:

1. Zvi Kohavi and Niraj K. Jha. Switching and Finite Automata Theory, 3 Editions, Cambridge University Press.
2. Zvi Kohavi, Switching Theory and Finite Automata, 2nd edition, Tata McGraw Hill
3. R. P. Jain, Switching Theory and Logic Design, Tata McGraw Hill Education, 2003.
4. Lee Samuel C., Modern Switching Theory and Digital Design, Prentice Hall PTR

Reference Books:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
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Internal Assessment:

Assessment consists of two class tests of 20 marks each. The first class test is to be conducted when approximately 40% syllabus is completed and second class test when additional 40% syllabus is completed. The average marks of both the test will be considered for final Internal Assessment. Duration of each test shall be of one hour.

End Semester Examination:

1. Question paper will comprise of 6 questions, each carrying 20 marks.
2. The students need to solve total 4 questions.
3. Question No.1 will be compulsory and based on entire syllabus.
4. Remaining question (Q.2 to Q.6) will be selected from all the modules.

For detail Syllabus of all subjects of Electronics & Telecommunication Engineering (EC) 5th Sem 2018 regulation, visit EC 5th Sem Subjects of 2018 Pattern.