ECCDLO7034: Cmos Mixed Signal Vlsi Syllabus for EC 7th Sem 2019 Pattern Mumbai University (Department Level Optional Course-3)

Cmos Mixed Signal Vlsi detailed syllabus scheme for Electronics & Telecommunication Engineering (EC), 2019 regulation has been taken from the MU official website and presented for the Bachelor of Engineering students. For Course Code, Course Title, Test 1, Test 2, Avg, End Sem Exam, Team Work, Practical, Oral, Total, and other information, do visit full semester subjects post given below.

For 7th Sem Scheme of Electronics & Telecommunication Engineering (EC), 2019 Pattern, do visit EC 7th Sem Scheme, 2019 Pattern. For the Department Level Optional Course-3 scheme of 7th Sem 2019 regulation, refer to EC 7th Sem Department Level Optional Course-3 Scheme 2019 Pattern. The detail syllabus for cmos mixed signal vlsi is as follows.

Cmos Mixed Signal Vlsi Syllabus for Electronics & Telecommunication Engineering BE 7th Sem 2019 Pattern Mumbai University

Prerequisites:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
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Course Objectives:

Importance of CMOS and Mixed Signal VLSI design in the field of Electronics and Telecommunication.
Underlying methodologies for analysis and design of fundamental CMOS Mixed signal Circuits like Data Converters.
The issues associated with high performance Mixed Signal VLSI Circuits

Course Outcomes:

After successful completion of the course student will be able to

Analyze and design single stage MOS Amplifiers.
Analyze and design Operational Amplifiers.
Analyze and design data converter circuits.
Identify design requirements of analog and mixed signal circuits
Analyze and design CMOS based switched capacitor circuits
Understand Oscillators and Phase Locked Loops.

Module 1

Module 2

Design of MOS operational amplifier 08

General considerations, One-Stage Op amps, Two-Stage Op amps, Gain Boosting, Input Range Limitation.
Frequency Response and Compensation, Slew Rate.

Module 3

Oscillators and Phase Locked Loops 08

General Considerations, Ring Oscillators, LC Oscillators, Voltage Controlled Oscillators (VCO), tuning range, tuning linearity Mathematical Model of VCO.
Simple PLL-phase detector, Charge-pump PLLs, Non ideal effects in PLL, Delay locked Loops, applications of PLL.

Module 4

Module 5

Data converters 06

Analog versus digital discrete time signals, converting analog signals to data signals, sample and hold characteristics. DAC specifications, ADC specifications.
Mixed signal Layout issues, Floor planning, power supply and Ground issues, other interconnect Considerations.

Module 6

Data Converter Architectures 10

DAC architectures: R-2R ladder networks, current steering, charge scaling DACs, Cyclic DAC, pipeline DAC, Switched capacitor based DAC design.
ADC architectures: flash, 2-step flash ADC, pipeline ADC, integrating ADC, and successive approximation ADC, Switched capacitor based ADC design

Text Books:

Internal Assessment:

Assessment consists of two class tests of 20 marks each. The first class test is to be conducted when approximately 40% syllabus is completed and second class test when additional 40% syllabus is completed. The average marks of both the test will be considered for final Internal Assessment. Duation of each test shall be of one hour.

End Semester Examination:

Question paper will comprise of 6 questions, each carrying 20 marks.
The students need to solve total 4 questions.
Question No.1 will be compulsory and based on entire syllabus.
Remaining question (Q.2 to Q.6) will be selected from all the modules.

For detail Syllabus of all subjects of Electronics & Telecommunication Engineering (EC) 7th Sem 2019 regulation, visit EC 7th Sem Subjects of 2019 Pattern.

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