Digital Vlsi Design detailed syllabus scheme for Electronics & Telecommunication Engineering (EC), 2018 regulation has been taken from the MU official website and presented for the Bachelor of Engineering students. For Course Code, Course Title, Test 1, Test 2, Avg, End Sem Exam, Team Work, Practical, Oral, Total, and other information, do visit full semester subjects post given below.
For 6th Sem Scheme of Electronics & Telecommunication Engineering (EC), 2018 Pattern, do visit EC 6th Sem Scheme, 2018 Pattern. For the Department Level Optional Course-2 scheme of 6th Sem 2018 regulation, refer to EC 6th Sem Department Level Optional Course-2 Scheme 2018 Pattern. The detail syllabus for digital vlsi design is as follows.
Digital Vlsi Design Syllabus for Electronics & Telecommunication Engineering TE 6th Sem 2018 Pattern Mumbai University
Prerequisites:
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Course Objectives:
- To highlight the circuit design issues in the context of Digital VLSI technology
- A profound understanding of Digital VLSI design circuits using different design styles.
- To provides an exposure to RTL design and programming
Course Outcomes:
After successful completion of the course student will be able to
- Understand the semiconductor technology, scaling and performance.
- Realize logic circuits with different design styles.
- To understand operation of memory, storage circuits and data path elements.
- Simulate and synthesize digital circuits using HDL language.
- Demonstrate an understanding of system level design issues such as protection, clocking, and routing.
- Learn the RTL design techniques and methodologies
Module 1
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Module 2
Memory and Storage circuits 08
- ROM array, SRAM (operation, design strategy, leakage currents, read /write circuits), layout of SRAM
- DRAM (Operation of 1T, 3T, operation modes, leakage currents, refresh operation, Input-Output circuits), layout of DRAM
- Flash memory: NAND and NOR flash memory
Module 3
Data path design 08
- Full adder, Ripple carry adder, CLA adder, Carry Skip Adder, Carry Save Adder and carry select adder
- Array Multiplier
- Barrel shifter
Module 4
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Module 5
Design methods 08
- Semicustom, Full custom design, ASIC
- PLA, PLD, PAL, FPGA
- System based and Data path design using HDL
Module 6
RTL Design 08
- High Level state machines, RTL design process
- Soda dispenser machine, laser based distance measure, Sum of absolute
- FIR filter design
Text Books:
For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier..
Reference Books:
- Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, Digital Integrated Circuits: A Design Perspective, Pearson Education, 2nd Edition.
- Volnei A. Pedroni /Circuit Design and Simulation with VHDL, MIT Press, 2nd Edition
Internal Assessment:
Assessment consists of two class tests of 20 marks each. The first class test is to be conducted when approximately 40% syllabus is completed and second class test when additional 40% syllabus is completed. The average marks of both the test will be considered for final Internal Assessment. Duration of each test shall be of one hour.
End Semester Examination:
- Question paper will comprise of 6 questions, each carrying 20 marks.
- The students need to solve total 4 questions.
- Question No.1 will be compulsory and based on entire syllabus.
- Remaining question (Q.2 to Q.6) will be selected from all the modules.
For detail Syllabus of all subjects of Electronics & Telecommunication Engineering (EC) 6th Sem 2018 regulation, visit EC 6th Sem Subjects of 2018 Pattern.