4th Sem, Computer Engg

CSL403: Processor Architecture Lab Syllabus for CS 4th Sem 2017 Pattern Mumbai University

Processor Architecture Lab detailed syllabus scheme for Computer Engineering (CS), 2017 regulation has been taken from the University of Mumbai official website and presented for the Bachelor of Engineering students. For Course Code, Course Title, Test 1, Test 2, Avg, End Sem Exam, Team Work, Practical, Oral, Total, and other information, do visit full semester subjects post given below.

For all other Mumbai University Computer Engineering 4th Sem Syllabus 2017 Pattern, do visit CS 4th Sem 2017 Pattern Scheme. The detailed syllabus scheme for processor architecture lab is as follows.

Processor Architecture Lab Syllabus for Computer Engineering SE 4th Sem 2017 Pattern Mumbai University

Processor Architecture Lab

Lab Objectives:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
Get it on Google Play.

Lab Outcomes:

At the end of the course student should be

  1. Assemble personal computer
  2. Design the basic building blocks of a computer: arithmetic-logic unit, registers, central processing unit, and memory.
  3. Implement various algorithms like Booths algorithm for arithmetic operations
  4. Describe various I/O buses with merits and demerits.

Prerequisites:

Digital Logic Design and Applications

Module 1

Overview of Computer Architecture & Organization

  • Computer Anatomy- Memory, Ports, Motherboard and add-on cards
  • Dismantling and assembling PC

Module 2

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
Get it on Google Play.

Module 3

Processor Organization and Architecture

  • ALU Design, CPU Design
  • Case Study on multi-core Processors

Module 4

Memory Organization

  • Memory design, Cache Memory design

Module 5

I/O Organization and Interrupts

  • Case study on buses like ISA, PCI, USB etc
  • Interrupt handling using C/Java Programming
  • Digital Material:

  • Manual to use the simulator for computer organization and architecture. Developed by the Department of CSE, IIT kharagpur (http://cse10-iitkgp.virtual-labs.ac.in/ )

Reference Books:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
Get it on Google Play.

For detail syllabus of all other subjects of Computer Engineering (CS) 4th Sem 2017 regulation, visit CS 4th Sem Subjects syllabus for 2017 regulation.

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