{"id":7016,"date":"2024-04-04T10:42:17","date_gmt":"2024-04-04T10:42:17","guid":{"rendered":"https:\/\/www.inspirenignite.com\/kl\/5209-verilog-hdl-pld-lab-syllabus-for-electronics-communication-engineering-5th-sem-2021-revision-sitttr\/"},"modified":"2024-04-04T10:42:17","modified_gmt":"2024-04-04T10:42:17","slug":"5209-verilog-hdl-pld-lab-syllabus-for-electronics-communication-engineering-5th-sem-2021-revision-sitttr","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/kl\/5209-verilog-hdl-pld-lab-syllabus-for-electronics-communication-engineering-5th-sem-2021-revision-sitttr\/","title":{"rendered":"5209: Verilog HDL & PLD Lab Syllabus for Electronics & Communication Engineering 5th Sem 2021 Revision SITTTR"},"content":{"rendered":"

Verilog HDL & PLD Lab detailed syllabus for Electronics & Communication Engineering (EC) for 2021 revision curriculum has been taken from the SITTTRs<\/a> official website and presented for the Electronics & Communication Engineering students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below. <\/p>\n

For Electronics & Communication Engineering 5th Sem scheme and its subjects, do visit Electronics & Communication Engineering (EC) 5th Sem 2021 revision scheme<\/a>. The detailed syllabus of verilog hdl & pld lab is as follows. <\/p>\n

Course Objectives:<\/h4>\n
    \n
  1. To introduce the simulation and test functional aspects of digital electronics circuits using Gate level, Data flow, Behavioural modelling of Verilog Hardware description language<\/li>\n
  2. To familiarize FPGA trainer kit<\/li>\n<\/ol>\n

    Course Outcomes:<\/h4>\n

    On completion of the course, the student will be able to :<\/p>\n

      \n
    1. Develop Verilog HDL program for designing combinational logic circuits using gate level modelling.<\/li>\n
    2. Develop Verilog HDL program for designing combinational and sequential logic circuits using data flow modelling.<\/li>\n
    3. Utilize behavioural modelling to design Sequential and Combinational logic circuits<\/li>\n
    4. Make use of FPGA \/ CPLD trainer kits to realize different combinational and sequential logic circuits<\/li>\n<\/ol>\n

      Module 1:<\/h4>\n
        \n
      1. Simulate and verify Verilog description of different logic gates<\/li>\n
      2. Simulate and verify Verilog description of Boolean expressions<\/li>\n
      3. Simulate and verify Verilog description for 1 bit full adder<\/li>\n
      4. Simulate and verify Verilog description for 4:1multiplexer<\/li>\n
      5. Simulate and verify Verilog description for 1:4demultiplexer<\/li>\n
      6. Simulate and verify Verilog description for 24 decoder<\/li>\n<\/ol>\n

        Module 2:<\/h4>\n
          \n
        1. Simulate and verify Verilog description for half adder using data flow operators.<\/li>\n
        2. Simulate and verify Verilog description for 1-bit full adder using data flow modelling<\/li>\n
        3. Simulate and verify Verilog description for 4:1 multiplexer using conditional operator<\/li>\n
        4. Simulate and verify Verilog description for 1:4 demultiplexer using logic equation<\/li>\n
        5. Simulate and verify Verilog description for D Flip Flop using data flow modelling<\/li>\n
        6. Simulate and verify Verilog description for T Flip Flop using data flow modelling<\/li>\n<\/ol>\n

          Module 3:<\/h4>\n
            \n
          1. Simulate and verify Verilog description for half subtractor and full subtractor using behavioural modelling<\/li>\n
          2. Simulate and verify Verilog description for 4:1 multiplexer using behavioural modelling<\/li>\n
          3. Simulate and verify Verilog description for JK Flip Flop using behavioural modelling<\/li>\n
          4. Simulate and verify Verilog description for 4 bitshift register using behavioural modelling<\/li>\n
          5. Simulate and verify Verilog description for 4 bitripple up counter using behavioural modelling<\/li>\n<\/ol>\n

            Module 4:<\/h4>\n
              \n
            1. Implement a 4-bit parallel adder using trainer kit<\/li>\n
            2. Implement binary to gray code converter using trainer kit<\/li>\n
            3. Implement BCD to 7 segment decoder using trainer kit<\/li>\n
            4. Implement a 4 bit Ripple up counter using a trainer kit<\/li>\n<\/ol>\n

              Text Books:<\/h4>\n
                \n
              1. Verilog HDL -Samir Palnitkar-Pearson Education<\/li>\n
              2. Digital design Morris mano, Third Edition, PHI<\/li>\n
              3. FPGA protyping by Verilog examples -PONG P Chu – Willey<\/li>\n<\/ol>\n

                Reference Books:<\/h4>\n
                  \n
                1. FPGA based system design Wayne Wolf, Pearson Education<\/li>\n
                2. T.R. Padmanabhan, B Bala Tripura Sundari, Design Through Verilog HDL, Wiley 2009.<\/li>\n
                3. HDL Programming- Nazeih M Botros- Dream Tech<\/li>\n
                4. Advanced Digital Logic Design using Verilog, State Machines & Synthesis for FPGA – Sunggu Lee, Cengage Learning, 2012.<\/li>\n
                5. Digital Systems Design with FPGAs and CPLDs -Ian Grout, Elsevier<\/li>\n<\/ol>\n

                  Online Recourses<\/h4>\n
                    \n
                  1. https:\/nptel.ac.in\/courses\/106\/105\/106105165\/<\/li>\n
                  2. https:\/\/www.tutorialspoint.com\/vlsi_design\/vlsi_design_verilog_introduction.h tm<\/li>\n
                  3. https:\/\/www.youtube.com\/watch?v=PJGvZSlsLKs<\/li>\n
                  4. https:\/\/www.youtube.com\/watch?v=pR6-aNxHNac<\/li>\n<\/ol>\n

                    Suggested Open Ended Experiments<\/h4>\n
                      \n
                    1. Develop Verilog HDL program for Traffic Signal Control for a junction where 4 roads meets.<\/li>\n
                    2. Design an 8 function ALU that takes 4 bits inputs A and B and a 3-bit input select, and gives a 5-bit output out.<\/li>\n
                    3. Develop a coffee vending machine using Verilog HDL programming.<\/li>\n<\/li>\n<\/ol>\n

                      For detailed syllabus of all other subjects of Electronics & Communication Engineering (EC), 2021 revision curriculum do visit Electronics & Communication Engineering 5th Sem subject syllabuses for 2021 revision<\/a>. <\/p>\n

                      To see the syllabus of all other branches of diploma 2021 revision curriculum do visit SITTTR diploma all branches syllabus.<\/a>. <\/p>\n

                      To see the results of Electronics & Communication Engineering (EC) of diploma 2021 revision curriculum do visit SITTTR diploma Electronics & Communication Engineering (EC) results.<\/a>. <\/p>\n

                      For all Electronics & Communication Engineering academic calendars, visit Electronics & Communication Engineering all semesters academic calendar<\/a> direct link. <\/p>\n","protected":false},"excerpt":{"rendered":"

                      Verilog HDL & PLD Lab detailed syllabus for Electronics & Communication Engineering (EC) for 2021 revision curriculum has been taken from the SITTTRs official website and presented for the Electronics […]<\/p>\n","protected":false},"author":2462,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[36,81],"tags":[],"class_list":["post-7016","post","type-post","status-publish","format-standard","hentry","category-5th-sem","category-ec"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/posts\/7016","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/users\/2462"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/comments?post=7016"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/posts\/7016\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/media?parent=7016"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/categories?post=7016"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/tags?post=7016"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}