{"id":2858,"date":"2021-06-20T03:27:23","date_gmt":"2021-06-20T03:27:23","guid":{"rendered":"https:\/\/www.inspirenignite.com\/kl\/6151-high-performance-computer-architecture-kl-diploma-syllabus-for-computer-hardware-6th-sem-2015-revision-sitttr\/"},"modified":"2021-06-20T03:27:23","modified_gmt":"2021-06-20T03:27:23","slug":"6151-high-performance-computer-architecture-kl-diploma-syllabus-for-computer-hardware-6th-sem-2015-revision-sitttr","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/kl\/6151-high-performance-computer-architecture-kl-diploma-syllabus-for-computer-hardware-6th-sem-2015-revision-sitttr\/","title":{"rendered":"6151: High Performance Computer Architecture KL Diploma Syllabus for Computer Hardware 6th Sem 2015 Revision SITTTR"},"content":{"rendered":"

High Performance Computer Architecture detailed syllabus for Computer Hardware (Computer Hardware) for 2015 revision curriculum has been taken from the SITTTRs<\/a> official website and presented for the Computer Hardware students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below. <\/p>\n

For Computer Hardware 6th Sem scheme and its subjects, do visit Computer Hardware 6th Sem 2015 revision scheme<\/a>. The detailed syllabus of high performance computer architecture is as follows. <\/p>\n

High Performance Computer Architecture<\/title><\/p>\n<h4>Course General Outcomes:<\/h4>\n<p id=\"istudy\" style=\"text-align:center\">For the complete syllabus, results, class timetable, and many other features kindly download the <a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">iStudy App<\/a><br \/><b> It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.<\/b><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px\"><\/a>. <\/p>\n<h4>Specific Outcomes:<\/h4>\n<p align=\"justify\">\n MODULE I Parallel Computer Models<\/p>\n<ol>\n<li>To Understand Parallel Computer Models\n<ol type=\"i\">\n<li>To explain Flynn’s Classification with diagram<\/li>\n<li>To discuss Parallel\/Vector computers<\/li>\n<li>To describe shared memory multiprocessors<\/li>\n<li>To explain UMA model with block diagram<\/li>\n<li>To describe distributed memory multicomputers<\/li>\n<li>To discuss Vector supercomputer<\/li>\n<li>To explain architecture of vector supercomputer<\/li>\n<li>To discuss SIMD supercomputer<\/li>\n<li>To explain operational model of SIMD supercomputer<\/li>\n<li>To discuss PRAM and VLSI models<\/li>\n<li>To explain PRAM model with diagram<\/li>\n<\/ol>\n<\/li>\n<li>To Understand Hardware and Software parallelism\n<ol type=\"i\">\n<li>To describe conditions of parallelism<\/li>\n<li>To discuss data dependence<\/li>\n<li>To discuss control dependence<\/li>\n<li>To discuss resource dependence<\/li>\n<li>To describe hardware and software parallelism<\/li>\n<li>To discuss hardware parallelism<\/li>\n<li>To discuss software parallelism<\/li>\n<li>To explain the mismatch between hardware and software parallelism<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n<p> MODULE II Advanced Processors and Memory Technology<\/p>\n<ol>\n<li>To Understand Advanced Processors and Memory Technology\n<ol type=\"i\">\n<li>To differentiate CISC and RISC Architectures<\/li>\n<li>To compare the architectural characteristics of CISC and RISC<\/li>\n<li>To discuss superscalar architecture<\/li>\n<li>To explain architecture of IBM RISC System\/6000 superscalar processor<\/li>\n<li>To explain VLIW architecture<\/li>\n<li>To explain pipelining in VLIW processors<\/li>\n<li>To discuss vector and symbolic Processors<\/li>\n<li>To explain Vector pipelines<\/li>\n<li>To explain symbolic processors<\/li>\n<li>To explain architecture of the Symbolic 6000 Lisp Processor<\/li>\n<li>To discuss four level Memory Hierarchy<\/li>\n<li>To discuss virtual memory models<\/li>\n<li>To explain private virtual memory<\/li>\n<li>To explain shared virtual memory<\/li>\n<\/ol>\n<\/li>\n<li>To Understand Cache and Shared Memory\n<ol type=\"i\">\n<li>To discuss cache addressing models<\/li>\n<li>To explain physical address caches<\/li>\n<li>To explain virtual address caches<\/li>\n<li>To discuss multi-level cache memories<\/li>\n<li>To discuss Interleaved memory organisation<\/li>\n<li>To explain memory interleaving<\/li>\n<li>To explain pipelined memory access<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n<p> MODULE III Pipelining and Superscalar Techniques<\/p>\n<ol>\n<li>To Understand different pipeline techniques\n<ol type=\"i\">\n<li>To discuss linear pipeline processors<\/li>\n<li>To explain asynchronous model<\/li>\n<li>To explain synchronous model<\/li>\n<li>To discuss nonlinear pipeline processors<\/li>\n<li>To explain Reservation tables and latency analysis<\/li>\n<li>To discuss instruction pipeline design<\/li>\n<li>To explain instruction pipeline phases<\/li>\n<li>To explain the mechanisms for instruction pipelining<\/li>\n<li>To discuss arithmetic pipeline design<\/li>\n<li>To explain static arithmetic pipelines<\/li>\n<li>To explain multifunctional arithmetic pipelines<\/li>\n<\/ol>\n<\/li>\n<li>To Understand Superscalar Pipeline Design\n<ol type=\"i\">\n<li>To describe superscalar pipeline design<\/li>\n<li>To explain superscalar pipeline structure<\/li>\n<li>To explain superscalar pipeline scheduling<\/li>\n<li>To explain the architecture of DEC Alpha 21064 processor<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n<p> MODULE IV Parallel And Scalable Architectures<\/p>\n<ol>\n<li>To Understand Multiprocessor and Multi computers\n<ol type=\"i\">\n<li>To describe hierarchical bus systems<\/li>\n<li>To explain Ultrmax multiprocessor architecture<\/li>\n<li>To discuss multi computer architectures<\/li>\n<li>To explain node architecture of multicomputer<\/li>\n<li>To explain router architecture of multicomputer<\/li>\n<\/ol>\n<\/li>\n<li>To Understand Multivector and SIMD Computers\n<ol type=\"i\">\n<li>To discuss vector processing principles<\/li>\n<li>To explain NEC SX-X 44 vector supercomputer architecture<\/li>\n<li>To explain distributed memory SIMD system model<\/li>\n<li>To explain shared memory SIMD system model<\/li>\n<\/ol>\n<\/li>\n<li>Multithreaded architecture\n<ol type=\"i\">\n<li>To explain multithreading issues and solutions<\/li>\n<li>To explain architecture of multiple context processor l<\/li>\n<li>To discuss multidimensional architecture<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n<h4>MODULE I – Parallel Computer Models<\/h4>\n<p id=\"istudy\" style=\"text-align:center\">For the complete syllabus, results, class timetable, and many other features kindly download the <a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">iStudy App<\/a><br \/><b> It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.<\/b><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px\"><\/a>. <\/p>\n<h4>MODULE II – Advanced Processor and Memory Technology<\/h4>\n<p align=\"justify\">\n Advanced processor technology::CISC and RISC scalar processorsSuperscalar architecture -VLIW architecture-pipelining in VLIW processors-Vector and symbolic processors-vector pipelines-Memory hierarchy technology-Virtual memory models-private and shared virtual memory. Cache and Shared Memory :: -Cache memory organization-Cache addressing models-Physical address caches-Virtual address caches-multi-level cache memories. Shared memory organization-interleaved memory organization-memory interleaving -pipelined memory access.\n<\/p>\n<h4>MODULE III – Pipelining and Superscalar Techniques<\/h4>\n<p id=\"istudy\" style=\"text-align:center\">For the complete syllabus, results, class timetable, and many other features kindly download the <a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">iStudy App<\/a><br \/><b> It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.<\/b><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px\"><\/a>. <\/p>\n<h4>MODULE IV – Parallel And Scalable Architectures<\/h4>\n<p align=\"justify\">\n Multiprocessors And Multicomputers:: Hierarchical bus systems-Multiprocessor architecture-multicomputer architecture -node and router architecture. Multivector and SIMD Computers:: -Vector supercomputer architecture. SIMD Computer organizations-Distributed memory model- Shared memory model. Multithreading processors::Multithreaded architecture-multithreading issues and solutions-multiple context processor-multidimensional architecture.\n<\/p>\n<h4>Text Books:<\/h4>\n<p id=\"istudy\" style=\"text-align:center\">For the complete syllabus, results, class timetable, and many other features kindly download the <a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">iStudy App<\/a><br \/><b> It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.<\/b><br \/><a class=\"rank-math-link\" href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy&pcampaignid=pcampaignidMKT-Other-global-all-co-prtnr-py-PartBadge-Mar2515-1\" target=\"_blank\" rel=\"noopener\"><img decoding=\"async\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" style=\"height:65px\"><\/a>. <\/p>\n<h4>Reference Books:<\/h4>\n<p align=\"justify\">\n<ol>\n<li>John L. Hennessey and David A. Patterson, Computer Architecture – A quantitative approach, Morgan Kaufmann \/ Elsevier, 4th. edition, 2007.<\/li>\n<li>David E. Culler, Jaswinder Pal Singh, Parallel Computing Architecture : A hardware\/ software approach , Morgan Kaufmann \/ Elsevier, 1997<\/li>\n<\/ol>\n<p align=\"justify\">For detailed syllabus of all other subjects of Computer Hardware, 2015 revision curriculum do visit <a class=\"rank-math-link\" href=\"..\/category\/computer-hardware+6th-sem\">Computer Hardware 6th Sem subject syllabuses for 2015 revision<\/a>. <\/p>\n<p align=\"justify\">To see the syllabus of all other branches of diploma 2015 revision curriculum do visit <a class=\"rank-math-link\" href=\"https:\/\/www.inspirenignite.com\/kl\/kerala-diploma-syllabus\/\">all branches of SITTTR diploma 2015 revision<\/a>. <\/p>\n","protected":false},"excerpt":{"rendered":"<p>High Performance Computer Architecture detailed syllabus for Computer Hardware (Computer Hardware) for 2015 revision curriculum has been taken from the SITTTRs official website and presented for the Computer Hardware students. […]<\/p>\n","protected":false},"author":2462,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[37,48],"tags":[],"class_list":["post-2858","post","type-post","status-publish","format-standard","hentry","category-6th-sem","category-computer-hardware"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/posts\/2858","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/users\/2462"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/comments?post=2858"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/posts\/2858\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/media?parent=2858"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/categories?post=2858"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/kl\/wp-json\/wp\/v2\/tags?post=2858"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}