6151: High Performance Computer Architecture KL Diploma Syllabus for Computer Hardware 6th Sem 2015 Revision SITTTR

High Performance Computer Architecture detailed syllabus for Computer Hardware (Computer Hardware) for 2015 revision curriculum has been taken from the SITTTRs official website and presented for the Computer Hardware students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below.

For Computer Hardware 6th Sem scheme and its subjects, do visit Computer Hardware 6th Sem 2015 revision scheme. The detailed syllabus of high performance computer architecture is as follows.

Course General Outcomes:

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Specific Outcomes:

MODULE I Parallel Computer Models

1. To Understand Parallel Computer Models
   1. To explain Flynn’s Classification with diagram
   2. To discuss Parallel/Vector computers
   3. To describe shared memory multiprocessors
   4. To explain UMA model with block diagram
   5. To describe distributed memory multicomputers
   6. To discuss Vector supercomputer
   7. To explain architecture of vector supercomputer
   8. To discuss SIMD supercomputer
   9. To explain operational model of SIMD supercomputer
   10. To discuss PRAM and VLSI models
   11. To explain PRAM model with diagram
2. To Understand Hardware and Software parallelism
   1. To describe conditions of parallelism
   2. To discuss data dependence
   3. To discuss control dependence
   4. To discuss resource dependence
   5. To describe hardware and software parallelism
   6. To discuss hardware parallelism
   7. To discuss software parallelism
   8. To explain the mismatch between hardware and software parallelism

MODULE II Advanced Processors and Memory Technology

1. To Understand Advanced Processors and Memory Technology
   1. To differentiate CISC and RISC Architectures
   2. To compare the architectural characteristics of CISC and RISC
   3. To discuss superscalar architecture
   4. To explain architecture of IBM RISC System/6000 superscalar processor
   5. To explain VLIW architecture
   6. To explain pipelining in VLIW processors
   7. To discuss vector and symbolic Processors
   8. To explain Vector pipelines
   9. To explain symbolic processors
   10. To explain architecture of the Symbolic 6000 Lisp Processor
   11. To discuss four level Memory Hierarchy
   12. To discuss virtual memory models
   13. To explain private virtual memory
   14. To explain shared virtual memory
2. To Understand Cache and Shared Memory
   1. To discuss cache addressing models
   2. To explain physical address caches
   3. To explain virtual address caches
   4. To discuss multi-level cache memories
   5. To discuss Interleaved memory organisation
   6. To explain memory interleaving
   7. To explain pipelined memory access

MODULE III Pipelining and Superscalar Techniques

1. To Understand different pipeline techniques
   1. To discuss linear pipeline processors
   2. To explain asynchronous model
   3. To explain synchronous model
   4. To discuss nonlinear pipeline processors
   5. To explain Reservation tables and latency analysis
   6. To discuss instruction pipeline design
   7. To explain instruction pipeline phases
   8. To explain the mechanisms for instruction pipelining
   9. To discuss arithmetic pipeline design
   10. To explain static arithmetic pipelines
   11. To explain multifunctional arithmetic pipelines
2. To Understand Superscalar Pipeline Design
   1. To describe superscalar pipeline design
   2. To explain superscalar pipeline structure
   3. To explain superscalar pipeline scheduling
   4. To explain the architecture of DEC Alpha 21064 processor

MODULE IV Parallel And Scalable Architectures

1. To Understand Multiprocessor and Multi computers
   1. To describe hierarchical bus systems
   2. To explain Ultrmax multiprocessor architecture
   3. To discuss multi computer architectures
   4. To explain node architecture of multicomputer
   5. To explain router architecture of multicomputer
2. To Understand Multivector and SIMD Computers
   1. To discuss vector processing principles
   2. To explain NEC SX-X 44 vector supercomputer architecture
   3. To explain distributed memory SIMD system model
   4. To explain shared memory SIMD system model
3. Multithreaded architecture
   1. To explain multithreading issues and solutions
   2. To explain architecture of multiple context processor l
   3. To discuss multidimensional architecture

MODULE I – Parallel Computer Models

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
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MODULE II – Advanced Processor and Memory Technology

Advanced processor technology::CISC and RISC scalar processorsSuperscalar architecture -VLIW architecture-pipelining in VLIW processors-Vector and symbolic processors-vector pipelines-Memory hierarchy technology-Virtual memory models-private and shared virtual memory. Cache and Shared Memory :: -Cache memory organization-Cache addressing models-Physical address caches-Virtual address caches-multi-level cache memories. Shared memory organization-interleaved memory organization-memory interleaving -pipelined memory access.

MODULE III – Pipelining and Superscalar Techniques

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
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MODULE IV – Parallel And Scalable Architectures

Multiprocessors And Multicomputers:: Hierarchical bus systems-Multiprocessor architecture-multicomputer architecture -node and router architecture. Multivector and SIMD Computers:: -Vector supercomputer architecture. SIMD Computer organizations-Distributed memory model- Shared memory model. Multithreading processors::Multithreaded architecture-multithreading issues and solutions-multiple context processor-multidimensional architecture.

Text Books:

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
.

Reference Books:

1. John L. Hennessey and David A. Patterson, Computer Architecture – A quantitative approach, Morgan Kaufmann / Elsevier, 4th. edition, 2007.
2. David E. Culler, Jaswinder Pal Singh, Parallel Computing Architecture : A hardware/ software approach , Morgan Kaufmann / Elsevier, 1997

For detailed syllabus of all other subjects of Computer Hardware, 2015 revision curriculum do visit Computer Hardware 6th Sem subject syllabuses for 2015 revision.

To see the syllabus of all other branches of diploma 2015 revision curriculum do visit all branches of SITTTR diploma 2015 revision.