Verilog HDL & Programmable Logic Devices detailed syllabus for Electronics Engineering (EL) for 2021 revision curriculum has been taken from the SITTTRs official website and presented for the Electronics Engineering (EL) students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below.
For Electronics Engineering 6th Sem scheme and its subjects, do visit Electronics Engineering (EL) 6th Sem 2021 regulation scheme. For Professional Elective-III scheme and its subjects refer to Electronics Engineering (EL) Professional Elective-III syllabus scheme. The detailed syllabus of verilog hdl & programmable logic devices is as follows.
Course Objectives:
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Course Outcomes:
On completion of the course, the student will be able to,
- Outline the basics of Hardware Description Language and program structure
- Make use of gate level modelling and dataflow modelling to design digital circuits
- Make use of Behavioural Modelling to design combinational and sequential circuits
- Outline the architecture of CPLDs and FPGA
Module 1:
Evolution of Computer Aided design, Overview of Digital design with Verilog HDL -Evolution of CAD – emergence of HDLs, typical HDL based design flow- why Verilog, trends in HDLs. Hierarchical Modelling Concepts – Top-down and bottom-up design methodology, differences between modules and module instances, components of a simulation. Design block, stimulus block, basic concepts, Lexical conventions, data types, system tasks, compiler directives. Module – Components of a Verilog module, Ports – definition, list of ports, port declaration, port connection rules
Module 2:
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Module 4:
Simple Programmable Logic Devices, Architecture of PAL and PAL ,compare PAL and PLA, Complex Programmable Logic Devices – Architecture and applications, Field Programmable Gate arrays – Architecture and applications, comparison of CPLD and FPGA, Concept of configurable logic blocks
Text Books:
For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
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- Verilog HDL -Samir Palnitkar-Pearson Education
- Digital design Morris mano, Third Edition, PHI
Reference Books:
- Digital Design | With an Introduction to the Verilog HDL, VHDL, and SystemVerilog | Sixth Edition | By Pearson Paperback -2018 by M. Morris Mano , Michael D.Ciletti
- FPGA based system design Wayne Wolf, Pearson Education
- T.R. Padmanabhan, B Bala Tripura Sundari, Design Through Verilog HDL, Wiley 2009.
- FPGA protyping by Verilog examples -PONG P Chu – Willey
- HDL Prgramming- Nazeih M Botros- Dream Tech
- Digital Systems Design with FPGAs and CPLDs -Ian Grout, Elsevier
Online Resources
For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier..
For detailed syllabus of all other subjects of Electronics Engineering, 2021 revision curriculum do visit Electronics Engineering (EL) 6th Sem subject syllabuses for 2021 revision.
To see the syllabus of all other branches of diploma 2021 revision curriculum do visit SITTTR diploma all branches syllabus..
To see the results of Electronics Engineering of diploma 2021 revision curriculum do visit SITTTR diploma results..
For all Electronics Engineering academic calendars, visit Electronics Engineering all semesters academic calendar direct link.