5209: Verilog HDL & PLD Lab Syllabus for Electronics & Communication Engineering 5th Sem 2021 Revision SITTTR

Verilog HDL & PLD Lab detailed syllabus for Electronics & Communication Engineering (EC) for 2021 revision curriculum has been taken from the SITTTRs official website and presented for the Electronics & Communication Engineering students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below.

For Electronics & Communication Engineering 5th Sem scheme and its subjects, do visit Electronics & Communication Engineering (EC) 5th Sem 2021 revision scheme. The detailed syllabus of verilog hdl & pld lab is as follows.

Course Objectives:

1. To introduce the simulation and test functional aspects of digital electronics circuits using Gate level, Data flow, Behavioural modelling of Verilog Hardware description language
2. To familiarize FPGA trainer kit

Course Outcomes:

On completion of the course, the student will be able to :

1. Develop Verilog HDL program for designing combinational logic circuits using gate level modelling.
2. Develop Verilog HDL program for designing combinational and sequential logic circuits using data flow modelling.
3. Utilize behavioural modelling to design Sequential and Combinational logic circuits
4. Make use of FPGA / CPLD trainer kits to realize different combinational and sequential logic circuits

Module 1:

1. Simulate and verify Verilog description of different logic gates
2. Simulate and verify Verilog description of Boolean expressions
3. Simulate and verify Verilog description for 1 bit full adder
4. Simulate and verify Verilog description for 4:1multiplexer
5. Simulate and verify Verilog description for 1:4demultiplexer
6. Simulate and verify Verilog description for 24 decoder

Module 2:

1. Simulate and verify Verilog description for half adder using data flow operators.
2. Simulate and verify Verilog description for 1-bit full adder using data flow modelling
3. Simulate and verify Verilog description for 4:1 multiplexer using conditional operator
4. Simulate and verify Verilog description for 1:4 demultiplexer using logic equation
5. Simulate and verify Verilog description for D Flip Flop using data flow modelling
6. Simulate and verify Verilog description for T Flip Flop using data flow modelling

Module 3:

1. Simulate and verify Verilog description for half subtractor and full subtractor using behavioural modelling
2. Simulate and verify Verilog description for 4:1 multiplexer using behavioural modelling
3. Simulate and verify Verilog description for JK Flip Flop using behavioural modelling
4. Simulate and verify Verilog description for 4 bitshift register using behavioural modelling
5. Simulate and verify Verilog description for 4 bitripple up counter using behavioural modelling

Module 4:

1. Implement a 4-bit parallel adder using trainer kit
2. Implement binary to gray code converter using trainer kit
3. Implement BCD to 7 segment decoder using trainer kit
4. Implement a 4 bit Ripple up counter using a trainer kit

Text Books:

1. Verilog HDL -Samir Palnitkar-Pearson Education
2. Digital design Morris mano, Third Edition, PHI
3. FPGA protyping by Verilog examples -PONG P Chu – Willey

Reference Books:

1. FPGA based system design Wayne Wolf, Pearson Education
2. T.R. Padmanabhan, B Bala Tripura Sundari, Design Through Verilog HDL, Wiley 2009.
3. HDL Programming- Nazeih M Botros- Dream Tech
4. Advanced Digital Logic Design using Verilog, State Machines & Synthesis for FPGA – Sunggu Lee, Cengage Learning, 2012.
5. Digital Systems Design with FPGAs and CPLDs -Ian Grout, Elsevier

Online Recourses

1. https:/nptel.ac.in/courses/106/105/106105165/
2. https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.h tm
3. https://www.youtube.com/watch?v=PJGvZSlsLKs
4. https://www.youtube.com/watch?v=pR6-aNxHNac

Suggested Open Ended Experiments

1. Develop Verilog HDL program for Traffic Signal Control for a junction where 4 roads meets.
2. Design an 8 function ALU that takes 4 bits inputs A and B and a 3-bit input select, and gives a 5-bit output out.
3. Develop a coffee vending machine using Verilog HDL programming.

For detailed syllabus of all other subjects of Electronics & Communication Engineering (EC), 2021 revision curriculum do visit Electronics & Communication Engineering 5th Sem subject syllabuses for 2021 revision.

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To see the results of Electronics & Communication Engineering (EC) of diploma 2021 revision curriculum do visit SITTTR diploma Electronics & Communication Engineering (EC) results..

For all Electronics & Communication Engineering academic calendars, visit Electronics & Communication Engineering all semesters academic calendar direct link.