{"id":231,"date":"2016-07-21T07:02:23","date_gmt":"2016-07-21T07:02:23","guid":{"rendered":"http:\/\/www.inspirenignite.com\/jntuk\/?p=231"},"modified":"2016-08-07T12:08:55","modified_gmt":"2016-08-07T12:08:55","slug":"jntuk-b-tech-vlsi-design-elective-i-for-r13-batch","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuk\/jntuk-b-tech-vlsi-design-elective-i-for-r13-batch\/","title":{"rendered":"JNTUK B.Tech VLSI Design (Elective \u2013 I) for R13 Batch."},"content":{"rendered":"<p>JNTUK B.Tech VLSI Design (Elective \u2013 I) R13 Syllabus for Engineering it gives you detail information about VLSI Design (Elective \u2013 I) syllabus.<\/p><div class=\"a9916ad81d5189659b0bfae0b37c143c\" data-index=\"1\" style=\"float: none; margin:10px 0 10px 0; text-align:center;\">\n<ins class=\"adsbygoogle\"\r\n     style=\"display:block; text-align:center;\"\r\n     data-ad-layout=\"in-article\"\r\n     data-ad-format=\"fluid\"\r\n     data-ad-client=\"ca-pub-1181153414625576\"\r\n     data-ad-slot=\"9648548092\"><\/ins>\r\n<script>\r\n     (adsbygoogle = window.adsbygoogle || []).push({});\r\n<\/script>\n<\/div>\n\n<p><strong>Preamble<\/strong><\/p>\n<p>In the recent times fabrication technology is revolutionized and especially LSI has become so dense that on a single IC tens and thousands of transistors are placed. Thus integrated circuits have become integrated systems and the development of fabrication technology VLSI plays very important role.<\/p>\n<p><strong>Learning Objectives<\/strong><\/p>\n<ul>\n<li>To provide the basic fundamentals of fabrication technology, generations of IC and speed, power consumptions of various fabrication technologies.<\/li>\n<li>To understand the knowledge of electrical properties of MOS circuits.<\/li>\n<li>To learn the design concepts of stick diagrams, layouts for various MOS technologies.<\/li>\n<li>To understand the concepts of design rules, scaling, subsystem design semiconductor IC design.<\/li>\n<li>To understand the synthesis, simulation design verification tools, CMOS testing.<\/li>\n<\/ul>\n<p><strong>UNIT \u2013I<\/strong><\/p>\n<p><strong>Introduction<\/strong> : Introduction to IC technology \u2013 The IC era \u2013 MOS and related VLSI technology \u2013 Basic MOS transistors \u2013 Enhancement and depletion modes of transistor action \u2013 IC production process \u2013 MOS and CMOS fabrication process \u2013 BiCMOS technology \u2013 Comparison b\/w CMOS and bipolar<br \/>\ntechnologies.<\/p>\n<p><strong>UNIT \u2013 II<\/strong><\/p>\n<p><strong>Basic electrical properties of MOS and BiCMOS circuits<\/strong> : Ids\u2013Vds relationships \u2013 Aspects of MOS transistor threshold voltage \u2013 MO Trans\u2013conductance and output conductance \u2013 MOS Transistor \u2013 Figure of merit \u2013 The pMOS transistor \u2013 The nMOS inverter \u2013 Determination of pull\u2013 up to pull\u2013down ratio for nMOS inverter driven by another nMOS inverter for an nMOS inverter driven through one or more pass Transistors \u2013 Alternative forms of pull up \u2013 The CMOS Inverter MOS transistor Circuit model \u2013 Bi\u2013CMOS Inverters.<\/p>\n<p><strong>UNIT \u2013 III<\/strong><\/p>\n<p><strong>MOS and BiCOMS circuit design processes :<\/strong> MOS layers \u2013 Stick diagrams \u2013 Design rules and layout \u2013 General observation on the design rules, 2\u03bcm double metal, double poly \u2013 CMOS\/BiCMOS rules, 1.2\u03bcm Double metal, Double poly CMOS rules \u2013 Layout diagrams of NAND and NOR gates and CMOS inverter \u2013 Symbolic Diagrams \u2013 Translation to Mask Form.<\/p>\n<p><strong>UNIT \u2013 IV<\/strong><\/p>\n<p><strong>Basic circuit concepts :<\/strong> Sheet resistance \u2013 Sheet resistance concept applied to MOS transistor and inverters \u2013 Area capacitance of layers \u2013 Standard unit of capacitance \u2013 Some area capacitance calculations \u2013 The delay unit \u2013 Inverter delays \u2013 Driving large capacitive loads \u2013 Propagations Delays \u2013 Wiring Capacitance \u2013 Fan\u2013in and Fan\u2013out characteristics \u2013 Choice of layers \u2013 Transistor switches \u2013 Realization of gates using nMOS, pMOS and CMOS technologies.<\/p>\n<p><strong>UNIT \u2013 V<\/strong><\/p>\n<p><strong>Scaling of MOS circuit \u00a0<\/strong>: Scaling models and scaling factors \u2013 Scaling factors for device parameters \u2013 Limitations of scaling \u2013 Limits due to sub threshold currents \u2013 Limits on logic level and supply voltage due to noise \u2013 Limits due to current density \u2013 Some architectural Issues \u2013 Introduction to switch logic and gate logic.<\/p>\n<p><strong>UNIT \u2013 VI<\/strong><\/p>\n<p><strong>Digital design using HDL<\/strong> : Digital system design process \u2013 VLSI Circuit Design Process \u2013 Hardware\u00a0simulation \u2013 Hardware Synthesis \u2013 History of VHDL \u2013 VHDL requirements \u2013 Levels of abstraction \u2013 Elements of VHDL \u2013 Packages \u2013 Libraries and bindings \u2013 Objects and classes \u2013 Variable assignments \u2013 Sequential statements \u2013 Usage of subprograms \u2013 Comparison of VHDL and verilog HDL.<\/p>\n<p><strong>VHDL MODELLING<\/strong> : Simulation \u2013 Logic Synthesis \u2013 Inside a logic synthesizer \u2013 Constraints \u2013 Technology libraries \u2013 VHDL and logic synthesis \u2013 Functional gate \u2013 Level verification \u2013 Place and route \u2013 Post layout timing simulation \u2013 Static timing \u2013 Major net list formats for design representation \u2013 VHDL synthesis \u2013 Programming approach.<\/p>\n<p><strong>Learning Outcomes<\/strong><\/p>\n<ul>\n<li>Ability to demonstrate the fundamentals of IC technology such as various MOS fabrication technologies.<\/li>\n<li>Ability to calculate electrical properties of MOS circuits such as Ids \u2013 Vds relationship, Vt, gm, gds, figure of merit, sheet resistance, area capacitance.<\/li>\n<li>Ability to demonstrate semi conductor IC design such as PLA\u2019s, PAL, FPGA, CPLS\u2019s design.<\/li>\n<li>Ability to demonstrate VHDL synthesis, simulation, design capture tools design verification tools, CMOS testing.<\/li>\n<\/ul>\n<p><strong>Text Books<\/strong><\/p>\n<ul>\n<li>Essentials of VLSI Circuits and Systems\u2013Kamran Eshraghian, Douglas and A.Pucknell and Sholeh Eshraghian, Prentice\u2013Hall of India Private Limited, 2005 Edition.<\/li>\n<li>VLSI Design\u2013K. Lal Kishor and V.S.V.Prabhakar, I.K. International Publishing House Private Limited, 2009 First Edition.<\/li>\n<li>VLSI Design\u2013A.Shanthi and A.Kavitha, New Age International Private Limited, 2006 First Edition.<\/li>\n<\/ul>\n<p><strong>References Books<\/strong><\/p>\n<ul>\n<li>VLSI Design By Debaprasad Das, Oxford University Press,2010.<\/li>\n<li>VLSI Design By A.Albert Raj &amp; T. Latha, PHI Learning Private Limited, 2010.<\/li>\n<\/ul>\n<p>For more information about all JNTU updates please stay connected to us on FB and don\u2019t hesitate to ask any questions in the comment.<\/p>\n<div class=\"a9916ad81d5189659b0bfae0b37c143c\" data-index=\"2\" style=\"float: none; margin:10px 0 10px 0; text-align:center;\">\n<ins class=\"adsbygoogle\"\r\n     style=\"display:block; text-align:center;\"\r\n     data-ad-layout=\"in-article\"\r\n     data-ad-format=\"fluid\"\r\n     data-ad-client=\"ca-pub-1181153414625576\"\r\n     data-ad-slot=\"8060844699\"><\/ins>\r\n<script>\r\n     (adsbygoogle = window.adsbygoogle || []).push({});\r\n<\/script>\n<\/div>\n\n<div style=\"font-size: 0px; height: 0px; line-height: 0px; margin: 0; padding: 0; clear: both;\"><\/div>","protected":false},"excerpt":{"rendered":"<p>JNTUK B.Tech VLSI Design (Elective \u2013 I) R13 Syllabus for Engineering it gives you detail information about VLSI Design (Elective \u2013 I) syllabus. Preamble In the recent times fabrication technology [&hellip;]<\/p>\n","protected":false},"author":2259,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[2],"tags":[],"class_list":["post-231","post","type-post","status-publish","format-standard","hentry","category-syllabus"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/jntuk\/wp-json\/wp\/v2\/posts\/231","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/jntuk\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/jntuk\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuk\/wp-json\/wp\/v2\/users\/2259"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuk\/wp-json\/wp\/v2\/comments?post=231"}],"version-history":[{"count":2,"href":"https:\/\/www.inspirenignite.com\/jntuk\/wp-json\/wp\/v2\/posts\/231\/revisions"}],"predecessor-version":[{"id":411,"href":"https:\/\/www.inspirenignite.com\/jntuk\/wp-json\/wp\/v2\/posts\/231\/revisions\/411"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/jntuk\/wp-json\/wp\/v2\/media?parent=231"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuk\/wp-json\/wp\/v2\/categories?post=231"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuk\/wp-json\/wp\/v2\/tags?post=231"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}