JNTUk B.Tech Digital Logic Design Lab R13 Syllabus for Engineering it gives you detail information about Digital Logic Design Lab syllabus.
List of Experiments
- Verification of Basic Logic Gates.
- Implementing all individual gates with Universal Gates NAND & NOR.
- Design a circuit for the given Canonical form, draw the circuit diagram and verify the De-Morgan laws.
- Design a Combinational Logic circuit for 4×1 MUX and verify the truth table.
- Design a Combinational Logic circuit for 1×4 De- MUX and verify the truth table.
- Verify the data read and data write operations for the IC 74189.
- Design a Gray code encoder and interface it to SRAM IC 74189 for write operation display on 7- segment.
- Design a Gray code De-coder and interface it to SRAM IC 74189 for read operation display it on 7- segment.
- Construct Half Adder and Full Adder using Half Adder and verify the truth table.
- Verification of truth tables of the basic Flip- Flops with Synchronous and Asynchronous modes.
- Implementation of Master Slave Flip-Flop with J-K Flip- Flop and verify the truth table for race around condition.
- Design a Decade Counter and verify the truth table.
- Design the Mod 6 counter using D-Flip -Flop.
- Construct 4-bit ring counter with T-Flip –Flop and verify the truth table.
- Design a 8 – bit right Shift Register using D-Flip -Flop and verify the truth table.
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