Digital Signal Processors and Architectures Detailed Syllabus for Digital Systems & Computer Electronics M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.<\/p>\n
The detailed syllabus for Digital Signal Processors and Architectures M.Tech 2017-2018 (R17) first year first sem is as follows.<\/p>\n
M.Tech. I Year I Sem.<\/p>\n
UNIT-I : Introduction to Digital Signal Processing:<\/strong> Introduction, A digital Signal \u2013 Processing system, the sampling process, Discrete time sequences, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), linear time-invariant systems, Digital filters, Decimation and interpolation. Architectures for Programmable DSP devices: Basic Architectural features, DSP computational building blocks, Bus Architecture and Memory, Data addressing capabilities, Address generation UNIT programmability and program execution, speed issues, features for external interfacing.<\/p>\n UNIT-II : Programmable Digital Signal Processors:<\/strong> Commercial Digital signal-processing Devices, Data Addressing modes of TMS320C54XX processors, memory space of TMS320C54XX processors, program control, TMS320C54XX instructions and programming, On-Chip peripherals, Interrupts of TMS320C54XX processors, Pipeline operation of TMS320C54XX processors.<\/p>\n UNIT-III <\/strong>: Architecture of ARM Processors:<\/strong> Introduction to the architecture, Programmer\u2019s model- operation modes and states, registers, special registers, floating point registers, Behavior of the application program status register(APSR)-Integer status flags, Q status flag, GE bits, Memory system-Memory system features, memory map, stack memory, memory protection unit (MPU), Exceptions and Interrupts-what are exceptions?, nested vectored interrupt controller(NVIC), vector table, Fault handling, System control block (SCB), Debug, Reset and reset sequence. Technical Details of ARM Processors: General information about Cortex-M3 and cortex M4 processors-Processor type, processor architecture, instruction set, block diagram, memory system, interrupt and exception support, Features of the cortex-M3 and Cortex-M4 Processors-Performance, code density, low power, memory system, memory protection unit, interrupt handling, OS support and system level features, Cortex-M4 specific features, Ease of use, Debug support, Scalability, Compatibility.<\/p>\n UNIT-IV : Instruction SET:<\/strong> Background to the instruction set in ARM Cortex-M Processors, Comparison of the instruction set in ARM Cortex-M Processors, understanding the assembly language syntax, Use of a suffix in instructions, Unified assembly Language (UAL), Instruction set, Cortex-M4-specific instructions, Barrel shifter, Accessing special instructions and special registers in Programming.<\/p>\n UNIT-V :<\/strong> Floating Point Operations:<\/strong> About Floating Point Data,Cortex-M4 Floating Point Unit (FPU)- overview, FP registers overview, CPACR register, Floating point register bank, FPSCR, FPU- >FPCCR, FPU-> FPCAR, FPU->FPDSCR, FPU->MVFR0, FPU->MVFR1.<\/p>\n TEXTBOOKS:<\/strong><\/p>\n REFERENCES:<\/strong><\/p>\n\n