{"id":9448,"date":"2018-08-29T15:25:30","date_gmt":"2018-08-29T15:25:30","guid":{"rendered":"https:\/\/www.inspirenignite.com\/jntuh\/?p=9448"},"modified":"2026-05-24T10:54:22","modified_gmt":"2026-05-24T05:24:22","slug":"jntuh-m-tech-2017-2018-r17-detailed-syllabus-cpld-and-fpga-architectures-and-application","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-m-tech-2017-2018-r17-detailed-syllabus-cpld-and-fpga-architectures-and-application\/","title":{"rendered":"JNTUH M.Tech 2017-2018 (R17) Detailed Syllabus CPLD and FPGA Architectures and Application"},"content":{"rendered":"CPLD and FPGA Architectures and Application Detailed Syllabus for Embedded Systems & VLSI Design\/ VLSI and Embedded Systems\/ Electronics Design Technology M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.\r\n\r\nThe detailed syllabus for CPLD and FPGA Architectures and Application M.Tech 2017-2018 (R17) first year first sem is as follows.\r\n\r\nM.Tech. I Year I Sem.\r\n\r\nUNIT-I : Introduction to Programmable Logic Devices:<\/strong>Introduction, Simple Programmable Logic Devices \u2013 Read Only Memories, Programmable Logic Arrays, Programmable Array Logic, Programmable Logic Devices\/Generic Array Logic; Complex Programmable Logic Devices \u2013 Architecture of Xilinx Cool Runner XCR3064XL CPLD, CPLD Implementation of a Parallel Adder with Accumulation.\r\n\r\nUNIT-II : Field Programmable Gate Arrays:<\/strong> Organization of FPGAs, FPGA Programming Technologies, Programmable Logic Block Architectures, Programmable Interconnects, Programmable I\/O blocks in FPGAs, Dedicated Specialized Components of FPGAs, Applications of FPGAs.\r\n\r\nUNIT \u2013III : SRAM Programmable FPGAs:<\/strong> Introduction, Programming Technology, Device Architecture, The Xilinx XC2000, XC3000 and XC4000 Architectures.\r\n\r\nUNIT \u2013IV : Anti-Fuse Programmed FPGAs:<\/strong> Introduction, Programming Technology, Device Architecture, The Actel ACT1, ACT2 and ACT3 Architectures.\r\n\r\nUNIT \u2013V : Design Applications:<\/strong> General Design Issues, Counter Examples, A Fast Video Controller, A Position Tracker for a Robot Manipulator, A Fast DMA Controller, Designing Counters with ACT devices, Designing Adders and Accumulators with the ACT Architecture.\r\n\r\nTEXT BOOKS:<\/strong>\r\n