CPLD and FPGA Architectures and Application Detailed Syllabus for Embedded Systems & VLSI Design\/ VLSI and Embedded Systems\/ Electronics Design Technology M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.<\/p>\n
The detailed syllabus for CPLD and FPGA Architectures and Application M.Tech 2017-2018 (R17) first year first sem is as follows.<\/p>\n
M.Tech. I Year I Sem.<\/p>\n
UNIT-I : Introduction to Programmable Logic Devices:<\/strong>Introduction, Simple Programmable Logic Devices \u2013 Read Only Memories, Programmable Logic Arrays, Programmable Array Logic, Programmable Logic Devices\/Generic Array Logic; Complex Programmable Logic Devices \u2013 Architecture of Xilinx Cool Runner XCR3064XL CPLD, CPLD Implementation of a Parallel Adder with Accumulation.<\/p>\n UNIT-II : Field Programmable Gate Arrays:<\/strong> Organization of FPGAs, FPGA Programming Technologies, Programmable Logic Block Architectures, Programmable Interconnects, Programmable I\/O blocks in FPGAs, Dedicated Specialized Components of FPGAs, Applications of FPGAs.<\/p>\n UNIT \u2013III : SRAM Programmable FPGAs:<\/strong> Introduction, Programming Technology, Device Architecture, The Xilinx XC2000, XC3000 and XC4000 Architectures.<\/p>\n UNIT \u2013IV : Anti-Fuse Programmed FPGAs:<\/strong> Introduction, Programming Technology, Device Architecture, The Actel ACT1, ACT2 and ACT3 Architectures.<\/p>\n UNIT \u2013V : Design Applications:<\/strong> General Design Issues, Counter Examples, A Fast Video Controller, A Position Tracker for a Robot Manipulator, A Fast DMA Controller, Designing Counters with ACT devices, Designing Adders and Accumulators with the ACT Architecture.<\/p>\n TEXT BOOKS:<\/strong><\/p>\n REFERENCE BOOKS:<\/strong><\/p>\n\n
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