{"id":9054,"date":"2018-08-25T18:34:04","date_gmt":"2018-08-25T18:34:04","guid":{"rendered":"https:\/\/www.inspirenignite.com\/jntuh\/?p=9054"},"modified":"2026-05-24T10:57:35","modified_gmt":"2026-05-24T05:27:35","slug":"jntuh-m-tech-2017-2018-r17-detailed-syllabus-vlsi-signal-processing","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-m-tech-2017-2018-r17-detailed-syllabus-vlsi-signal-processing\/","title":{"rendered":"JNTUH M.Tech 2017-2018 (R17) Detailed Syllabus VLSI Signal Processing"},"content":{"rendered":"VLSI Signal Processing Detailed Syllabus for Systems and Signal Processing M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.\r\n\r\nThe detailed syllabus for VLSI Signal Processing M.Tech 2017-2018 (R17) first year first sem is as follows.\r\n\r\nM.Tech. I Year I Sem.\r\n\r\nUNIT -I : Introduction to DSP:<\/strong> Typical DSP algorithms, DSP algorithms benefits, Representation of DSP algorithms. Pipelining and Parallel Processing: Introduction, Pipelining of FIR Digital filters, Parallel Processing, Pipelining and Parallel Processing for Low Power. Retiming: Introduction \u2013 Definitions and Properties \u2013 Solving System of Inequalities \u2013 Retiming Techniques.\r\n\r\nUNIT \u2013II : Folding and Unfolding:<\/strong> Folding: Introduction -Folding Transform – Register minimization Techniques \u2013 Register minimization in folded architectures \u2013 folding of multirate systems Unfolding: Introduction \u2013 An Algorithm for Unfolding \u2013 Properties of Unfolding \u2013 critical Path, Unfolding and Retiming \u2013 Applications of Unfolding\r\n\r\nUNIT -III : Systolic Architecture Design:<\/strong> Introduction \u2013 Systolic Array Design Methodology \u2013 FIR Systolic Arrays \u2013 Selection of Scheduling Vector \u2013 Matrix Multiplication and 2D Systolic Array Design \u2013 Systolic Design for Space Representations contain Delays\r\n\r\nUNIT -IV : Fast Convolution:<\/strong> Introduction \u2013 Cook-Toom Algorithm \u2013 Winogard algorithm \u2013 Iterated Convolution \u2013 Cyclic Convolution \u2013 Design of Fast Convolution algorithm by Inspection\r\n\r\nUNIT -V : Low Power Design:<\/strong> Scaling Vs Power Consumption \u2013Power Analysis, Power Reduction techniques \u2013 Power Estimation Approaches. Programmable DSP: Evaluation of Programmable Digital Signal Processors, DSP Processors for Mobile and Wireless Communications, Processors for Multimedia Signal Processing\r\n\r\nTEXT BOOKS:<\/strong>\r\n