{"id":9010,"date":"2018-08-25T13:55:09","date_gmt":"2018-08-25T13:55:09","guid":{"rendered":"https:\/\/www.inspirenignite.com\/jntuh\/?p=9010"},"modified":"2021-10-28T15:44:41","modified_gmt":"2021-10-28T15:44:41","slug":"jntuh-m-tech-2017-2018-r17-detailed-syllabus-digital-ic-design-lab","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-m-tech-2017-2018-r17-detailed-syllabus-digital-ic-design-lab\/","title":{"rendered":"JNTUH M.Tech 2017-2018 (R17) Detailed Syllabus Digital IC Design Lab"},"content":{"rendered":"

Digital IC Design Lab Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.<\/p>\n

The detailed syllabus for Digital IC Design Lab M.Tech 2017-2018 (R17) first year first sem is as follows.<\/p>\n

M.Tech. I Year I Sem.<\/p>\n

Part \u2013I<\/strong>
\nProgramming can be done using any complier. Down load the programs on FPGA\/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools.<\/p>\n

    \n
  1. HDL code to realize all the logic gates<\/li>\n
  2. Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry<\/li>\n
  3. Look Ahead Adder.<\/li>\n
  4. Design of 2-to-4 decoder<\/li>\n
  5. Design of 8-to-3 encoder (without and with parity)<\/li>\n
  6. Design of 8-to-1 multiplexer<\/li>\n
  7. Design of 4 bit binary to gray converter<\/li>\n
  8. Design of Multiplexer\/ Demultiplexer, comparator<\/li>\n
  9. Design of Full adder using 3 modeling styles<\/li>\n
  10. Design of flip flops: SR, D, JK, T<\/li>\n
  11. Design of 4-bit binary, BCD counters ( synchronous\/ asynchronous reset) or any sequence counter<\/li>\n
  12. Design of a N- bit Register of Serial- in Serial \u2013out, Serial in parallel out, Parallel in<\/li>\n
  13. Serial out and Parallel in Parallel Out.<\/li>\n
  14. Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).<\/li>\n
  15. Design of 4- Bit Multiplier, Divider.<\/li>\n
  16. Design of ALU to Perform \u2013 ADD, SUB, AND-OR, 1\u2019s and 2\u2019s Compliment,<\/li>\n
  17. Multiplication, and Division.<\/li>\n
  18. Design of Finite State Machine.<\/li>\n
  19. Implementing the above designs on Xilinx\/Altera\/Cypress\/equivalent based FPGA\/CPLD kits<\/li>\n<\/ol>\n

    Part \u2013II<\/strong><\/p>\n

      \n
    1. Static and Dynamic Characteristics of CMOS Inverter<\/li>\n
    2. Implementation of EX-OR gate using complementary CMOS, Psedo-NMOS, Dynamic and domino logic style<\/li>\n
    3. Implementation of Full Adder using Transmission Gates<\/li>\n<\/ol>\n

      For all other M.Tech 1st Year 1st Sem syllabus go to JNTUH M.Tech VLSI\/ VLSI Design\/VLSI System Design 1st Year 1st Sem Course Structure for (R17) Batch.<\/a><\/p>\n

      All details and yearly new syllabus will be updated here time to time. Subscribe, like us on facebook and follow us on google plus for all updates.<\/p>\n

      Do share with friends and in case of questions please feel free drop a comment.<\/p>\n","protected":false},"excerpt":{"rendered":"

      Digital IC Design Lab Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and […]<\/p>\n","protected":false},"author":2259,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[62,73],"tags":[],"class_list":["post-9010","post","type-post","status-publish","format-standard","hentry","category-syllabus","category-m-tech"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/9010","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/users\/2259"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/comments?post=9010"}],"version-history":[{"count":3,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/9010\/revisions"}],"predecessor-version":[{"id":13946,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/9010\/revisions\/13946"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/media?parent=9010"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/categories?post=9010"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/tags?post=9010"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}