{"id":9008,"date":"2018-08-25T13:49:30","date_gmt":"2018-08-25T13:49:30","guid":{"rendered":"https:\/\/www.inspirenignite.com\/jntuh\/?p=9008"},"modified":"2026-05-24T10:58:05","modified_gmt":"2026-05-24T05:28:05","slug":"jntuh-m-tech-2017-2018-r17-detailed-syllabus-advanced-computer-architecture","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-m-tech-2017-2018-r17-detailed-syllabus-advanced-computer-architecture\/","title":{"rendered":"JNTUH M.Tech 2017-2018 (R17) Detailed Syllabus Advanced Computer Architecture"},"content":{"rendered":"Advanced Computer Architecture Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.\r\n\r\nThe detailed syllabus for Advanced Computer Architecture M.Tech 2017-2018 (R17) first year first sem is as follows.\r\n\r\nM.Tech. I Year I Sem.\r\n\r\nUNIT- I : Fundamentals of Computer Design:<\/strong> Fundamentals of Computer design, Changing faces of computing and task of computer designer, Technology trends, Cost price and their trends, measuring and reporting performance, quantitative principles of computer design, Amdahl\u2019s law. Instruction set principles and examples- Introduction, classifying instruction set- memory addressing type and size of operands, operations in the instruction set.\r\n\r\nUNIT \u2013 II : Pipelines:<\/strong> Introduction ,basic RISC instruction set ,Simple implementation of RISC instruction set, Classic five stage pipe line for RISC processor, Basic performance issues in pipelining , Pipeline hazards, Reducing pipeline branch penalties. Memory Hierarchy Design: Introduction, review of ABC of cache, Cache performance , Reducing cache miss penalty, Virtual memory.\r\n\r\nUNIT – III : Instruction Level Parallelism the Hardware Approach:<\/strong> Instruction-Level parallelism, Dynamic scheduling, Dynamic scheduling using Tomasulo\u2019s approach, Branch prediction, high performance instruction delivery- hardware based speculation. ILP Software Approach: Basic compiler level techniques, static branch prediction, VLIW approach, Exploiting ILP, Parallelism at compile time, Cross cutting issues -Hardware verses Software.\r\n\r\nUNIT \u2013 IV : Multi Processors and Thread Level Parallelism:<\/strong> Multi Processors and Thread level Parallelism Introduction, Characteristics of application domain, Systematic shared memory architecture, Distributed shared \u2013 memory architecture, Synchronization.\r\n\r\nUNIT \u2013 V : Inter Connection and Networks:<\/strong> Introduction, Interconnection network media, Practical issues in interconnecting networks, Examples of inter connection, Cluster, Designing of clusters. Intel Architecture: Intel IA- 64 ILP in embedded and mobile markets Fallacies and pit falls\r\n\r\nTEXT BOOKS:<\/strong>\r\n