Algorithms for VLSI Design Automation Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.<\/p>\n
The detailed syllabus for Algorithms for VLSI Design Automation M.Tech 2017-2018 (R17) first year first sem is as follows.<\/p>\n
M.Tech. I Year I Sem.<\/p>\n
UNIT- I : PRELIMINARIES:<\/strong> Introduction to Design Methodologies, Design Automation tools, Algorithmic Graph Theory, Computational complexity, Tractable and Intractable problems.<\/p>\n UNIT -II : GENERAL PURPOSE METHODS FOR COMBINATIONAL OPTIMIZATION:<\/strong> Backtracking, Branch and Bound, Dynamic Programming, Integer Linear Programming, Local Search, Simulated Annealing, Tabu search, Genetic Algorithms.<\/p>\n UNIT- III : LAYOUT COMPACTION, PLACEMENT, FLOOR PLANNING AND ROUTING:<\/strong> Problems, Concepts and Algorithms. UNIT -IV : LOGIC SYNTHESIS AND VERIFICATION:<\/strong> Basic issues and Terminology, Binary-Decision diagrams, Two-Level logic Synthesis. UNIT- V : PHYSICAL DESIGN AUTOMATION OF FPGAs:<\/strong> FPGA technologies, Physical Design cycle for FPGAs, partitioning and Routing for segmented and staggered Models. PHYSICAL DESIGN AUTOMATION OF MCMs : MCM technologies, MCM physical design cycle, Partitioning, Placement – Chip Array based and Full Custom Approaches, Routing \u2013 Maze routing, Multiple stage routing, Topologic routing, Integrated Pin \u2013 Distribution and routing, Routing and Programmable MCMs.<\/p>\n TEXT BOOKS:<\/strong><\/p>\n REFERENCE BOOKS:<\/strong><\/p>\n
\nMODELLING AND SIMULATION:<\/strong> Gate Level Modelling and Simulation, Switch level Modelling and Simulation.<\/p>\n
\nHIGH-LEVEL SYNTHESIS:<\/strong> Hardware Models, Internal representation of the input Algorithm, Allocation, Assignment and Scheduling, Some Scheduling Algorithms, Some aspects of Assignment problem, High-level Transformations.<\/p>\n\n
\n