{"id":8991,"date":"2018-08-25T12:54:58","date_gmt":"2018-08-25T12:54:58","guid":{"rendered":"https:\/\/www.inspirenignite.com\/jntuh\/?p=8991"},"modified":"2021-10-28T15:45:41","modified_gmt":"2021-10-28T15:45:41","slug":"jntuh-m-tech-2017-2018-r17-detailed-syllabus-vlsi-technology","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-m-tech-2017-2018-r17-detailed-syllabus-vlsi-technology\/","title":{"rendered":"JNTUH M.Tech 2017-2018 (R17) Detailed Syllabus VLSI Technology"},"content":{"rendered":"<p>VLSI Technology Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.<\/p>\n<p>The detailed syllabus for VLSI Technology M.Tech 2017-2018 (R17) first year first sem is as follows.<\/p>\n<p>M.Tech. I Year I Sem.<\/p>\n<p><strong>UNIT \u2013I : Review of Microelectronics and Introduction to MOS Technologies:<\/strong> MOS, CMOS, BiCMOS Technology. Basic Electrical Properties of MOS, CMOS &amp; BiCMOS Circuits: Ids \u2013 Vds relationships, Threshold Voltage VT, Gm, Gds and \u03c9o, Pass Transistor, MOS, CMOS &amp; Bi CMOS Inverters, Zpu\/Zpd, MOS Transistor circuit model, Latch-up in CMOS circuits.<\/p>\n<p><strong>UNIT \u2013II : Layout Design and Tools:<\/strong> Transistor structures, Wires and Vias, Scalable Design rules, Layout Design tools. Logic Gates &amp; Layouts: Static Complementary Gates, Switch Logic, Alternative Gate circuits, Low power gates, Resistive and Inductive interconnect delays.<\/p>\n<p><strong>UNIT \u2013III : Overview of semiconductor industry,<\/strong> Stages of Manufacturing, Process and product trends, Crystal growth, Basic wafer fabrication operations, process yields, Semiconductor material preparation, Basic wafer fabrication operations, Yield measurement, Contamination sources, Clean room construction, Oxidation and Photolithography, Doping and Depositions, Metallization.Ten step patterning process, Photoresists, physical properties of photoresists, Storage and control of photoresists, photo masking process, Hard bake, develop inspect, Dry etching Wet etching, resist stripping<\/p>\n<p><strong>UNIT \u2013IV : Doping and depositions<\/strong>: Diffusion process steps, deposition, Drive-in oxidation, Ion implantation-1, Ion implantation-2, CVD basics, CVD process steps, Low pressure CVD systems, Plasma enhanced CVD systems, Vapour phase epitoxy, molecular beam epitaxy.<\/p>\n<p><strong>UNIT \u2013V : Design rules and Scaling, BICMOS ICs:<\/strong> Choice of transistor types, pnp transistors, Resistors, capacitors, Packaging: Chip characteristics, package functions, package operations<\/p>\n<p><strong>TEXT BOOKS:<\/strong><\/p>\n<ul>\n<li>Peter Van Zant, \u201cMicrochip fabrication\u201d, McGraw Hill, 1997.<\/li>\n<li>C.Y. Chang and S.M. Sze, \u201cULSI technology\u201d, McGraw Hill, 2000<\/li>\n<\/ul>\n<p><strong>REFERENCE BOOKS:<\/strong><\/p>\n<ul>\n<li>Muhammad H Rashid, \u201cMicro Electronics circuits Analysis and Design\u201d, 2nd Edition, CENAGE Learning, 2011.<\/li>\n<li>Eugene D. Fabricius, \u201cIntroduction to VLSI design\u201d, McGraw Hill, 1999<\/li>\n<li>Wani-Kai Chen (editor), \u201cThe VLSI Hand book\u201d, CRI\/IEEE press, 2000<\/li>\n<li>S.K. Gandhi, \u201cVLSI Fabrication principles\u201d, John Wiley and Sons, NY, 1994<\/li>\n<\/ul>\n<p>For all other M.Tech 1st Year 1st Sem syllabus go to <a href=\"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-first-year-first-sem-vlsi-vlsi-design-vlsi-system-design-for-m-tech-2017-2018-r17-batch\/\">JNTUH M.Tech VLSI\/ VLSI Design\/VLSI System Design 1st Year 1st Sem Course Structure for (R17) Batch.<\/a><\/p>\n<p>All details and yearly new syllabus will be updated here time to time. Subscribe, like us on facebook and follow us on google plus for all updates.<\/p>\n<p>Do share with friends and in case of questions please feel free drop a comment.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>VLSI Technology Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details [&hellip;]<\/p>\n","protected":false},"author":2259,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[73,62],"tags":[],"class_list":["post-8991","post","type-post","status-publish","format-standard","hentry","category-m-tech","category-syllabus"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/8991","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/users\/2259"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/comments?post=8991"}],"version-history":[{"count":2,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/8991\/revisions"}],"predecessor-version":[{"id":13938,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/8991\/revisions\/13938"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/media?parent=8991"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/categories?post=8991"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/tags?post=8991"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}