{"id":8984,"date":"2018-08-25T12:34:57","date_gmt":"2018-08-25T12:34:57","guid":{"rendered":"https:\/\/www.inspirenignite.com\/jntuh\/?p=8984"},"modified":"2026-05-24T10:58:17","modified_gmt":"2026-05-24T05:28:17","slug":"jntuh-m-tech-2017-2018-r17-detailed-syllabus-advanced-digital-system-design","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-m-tech-2017-2018-r17-detailed-syllabus-advanced-digital-system-design\/","title":{"rendered":"JNTUH M.Tech 2017-2018 (R17) Detailed Syllabus Advanced Digital System Design"},"content":{"rendered":"Advanced Digital System Design Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.\r\n\r\nThe detailed syllabus for Advanced Digital System Design M.Tech 2017-2018 (R17) first year first sem is as follows.\r\n\r\nM.Tech. I Year I Sem.\r\n\r\n<strong>UNIT &#8211; I : Processor Arithmetic:<\/strong> Two&#8217;s Complement Number System &#8211; Arithmetic Operations; Fixed point Number System; Floating Point Number system &#8211; IEEE 754 format, Basic binary codes.\r\n\r\n<strong>UNIT &#8211; II : Combinational circuits:<\/strong> CMOS logic design, Static and dynamic analysis of Combinational circuits, timing hazards. Functional blocks &#8211; Decoders, Encoders, Three-state devices, Multiplexers, Parity circuits, Comparators, Adders, Subtractors, Carrylook- ahead adder \u2013 timing analysis .Combinational multiplier structures.\r\n\r\n<strong>UNIT &#8211; III : Sequential Logic:<\/strong> Latches and Flip-Flops, Sequential logic circuits &#8211; timing analysis (Set up and hold times), State machines &#8211; Mealy &amp; Moore machines, Analysis, FSM design using D Flip-Flops, FSM optimization and partitioning; Synchronizers and metastability. FSM Design examples: Vending machine, Traffic light controller, Washing machine.\r\n\r\n<strong>UNIT &#8211; IV : Subsystem Design using Functional Blocks (1):<\/strong> Design (including Timing Analysis) of different logical blocks of varying complexities involving mostly combinational circuits:\r\n<ul>\r\n \t<li>ALU<\/li>\r\n \t<li>4-bit combinational multiplier<\/li>\r\n \t<li>Barrel shifter<\/li>\r\n \t<li>Simple fixed point to floating point encoder<\/li>\r\n \t<li>Dual Priority encoder<\/li>\r\n \t<li>Cascading comparators<\/li>\r\n<\/ul>\r\n<strong>UNIT &#8211; V : Subsystem Design using Functional Blocks (2):<\/strong> Design, (including Timing Analysis) of different logical blocks of different complexities involving mostly sequential circuits:\r\n<ul>\r\n \t<li>Pattern (sequence) detector<\/li>\r\n \t<li>Programmable Up-down counter<\/li>\r\n \t<li>Round robin arbiter with 3 requesters<\/li>\r\n \t<li>Process Controller<\/li>\r\n \t<li>FIFO<\/li>\r\n<\/ul>\r\n<strong>TEXT BOOKS:<\/strong>\r\n<ul>\r\n \t<li>John F. Wakerly, \u201cDigital Design\u201d, Prentice Hall, 3rd Edition, 2002<\/li>\r\n<\/ul>\r\n<strong>*Note1:<\/strong> VHDL and ABEL are not part of this course.\r\n<strong>*Note2:<\/strong> SSI &amp; MSI ICs listed in data books are not part of this course\r\n\r\nFor all other M.Tech 1st Year 1st Sem syllabus go to <a href=\"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-first-year-first-sem-vlsi-vlsi-design-vlsi-system-design-for-m-tech-2017-2018-r17-batch\/\">JNTUH M.Tech VLSI\/ VLSI Design\/VLSI System Design 1st Year 1st Sem Course Structure for (R17) Batch.<\/a>\r\n\r\nAll details and yearly new syllabus will be updated here time to time. Subscribe, like us on facebook and follow us on google plus for all updates.\r\n\r\nDo share with friends and in case of questions please feel free drop a comment.\n\n<h2>Download iStudy App (Android &amp; iOS)<\/h2>\n<div style=\"width: 100%;text-align: center;background: #f0f7ff;border: 1px solid #d9e8ff;border-radius: 10px;padding: 12px 10px;margin: 8px 0 12px 0\">\n<p style=\"margin: 0 0 8px 0\">Get instant JNTUH updates, timetables, results, and notices on mobile.<\/p>\n<div style=\"justify-content: center;align-items: flex-start;gap: 24px;flex-wrap: wrap\">\n<div style=\"flex-direction: column;align-items: center;gap: 2px\"><img decoding=\"async\" style=\"height: 54px;width: auto\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" \/>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\u00a0<img decoding=\"async\" style=\"height: 80px;width: 80px\" src=\"https:\/\/api.qrserver.com\/v1\/create-qr-code\/?size=120x120&amp;data=https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" alt=\"Android app QR code\" \/><\/div>\n<div>\u00a0<\/div>\n<div style=\"flex-direction: column;align-items: center;gap: 2px\"><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">Android App<\/a><\/div>\n<div>\u00a0<\/div>\n<div style=\"flex-direction: column;align-items: center;gap: 2px\"><img decoding=\"async\" style=\"height: 40px;width: auto\" src=\"https:\/\/upload.wikimedia.org\/wikipedia\/commons\/3\/3c\/Download_on_the_App_Store_Badge.svg\" alt=\"Download on the App Store\" \/>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\u00a0<img decoding=\"async\" style=\"height: 80px;width: 80px\" src=\"https:\/\/api.qrserver.com\/v1\/create-qr-code\/?size=120x120&amp;data=https:\/\/apps.apple.com\/us\/app\/istudy-app-syllabus-papers\/id6478500231\" alt=\"iOS app QR code\" \/><\/div>\n<div>\u00a0<\/div>\n<div style=\"flex-direction: column;align-items: center;gap: 2px\"><a href=\"https:\/\/apps.apple.com\/us\/app\/istudy-app-syllabus-papers\/id6478500231\" target=\"_blank\" rel=\"noopener\">iOS App <\/a><\/div>\n<\/div>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Advanced Digital System Design Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and [&hellip;]<\/p>\n","protected":false},"author":2259,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[73,62],"tags":[],"class_list":["post-8984","post","type-post","status-publish","format-standard","hentry","category-m-tech","category-syllabus"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/8984","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/users\/2259"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/comments?post=8984"}],"version-history":[{"count":3,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/8984\/revisions"}],"predecessor-version":[{"id":40641,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/8984\/revisions\/40641"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/media?parent=8984"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/categories?post=8984"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/tags?post=8984"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}