{"id":8984,"date":"2018-08-25T12:34:57","date_gmt":"2018-08-25T12:34:57","guid":{"rendered":"https:\/\/www.inspirenignite.com\/jntuh\/?p=8984"},"modified":"2021-10-27T22:42:10","modified_gmt":"2021-10-27T22:42:10","slug":"jntuh-m-tech-2017-2018-r17-detailed-syllabus-advanced-digital-system-design","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-m-tech-2017-2018-r17-detailed-syllabus-advanced-digital-system-design\/","title":{"rendered":"JNTUH M.Tech 2017-2018 (R17) Detailed Syllabus Advanced Digital System Design"},"content":{"rendered":"<p>Advanced Digital System Design Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.<\/p>\n<p>The detailed syllabus for Advanced Digital System Design M.Tech 2017-2018 (R17) first year first sem is as follows.<\/p>\n<p>M.Tech. I Year I Sem.<\/p>\n<p><strong>UNIT &#8211; I : Processor Arithmetic:<\/strong> Two&#8217;s Complement Number System &#8211; Arithmetic Operations; Fixed point Number System; Floating Point Number system &#8211; IEEE 754 format, Basic binary codes.<\/p>\n<p><strong>UNIT &#8211; II : Combinational circuits:<\/strong> CMOS logic design, Static and dynamic analysis of Combinational circuits, timing hazards. Functional blocks &#8211; Decoders, Encoders, Three-state devices, Multiplexers, Parity circuits, Comparators, Adders, Subtractors, Carrylook- ahead adder \u2013 timing analysis .Combinational multiplier structures.<\/p>\n<p><strong>UNIT &#8211; III : Sequential Logic:<\/strong> Latches and Flip-Flops, Sequential logic circuits &#8211; timing analysis (Set up and hold times), State machines &#8211; Mealy &amp; Moore machines, Analysis, FSM design using D Flip-Flops, FSM optimization and partitioning; Synchronizers and metastability. FSM Design examples: Vending machine, Traffic light controller, Washing machine.<\/p>\n<p><strong>UNIT &#8211; IV : Subsystem Design using Functional Blocks (1):<\/strong> Design (including Timing Analysis) of different logical blocks of varying complexities involving mostly combinational circuits:<\/p>\n<ul>\n<li>ALU<\/li>\n<li>4-bit combinational multiplier<\/li>\n<li>Barrel shifter<\/li>\n<li>Simple fixed point to floating point encoder<\/li>\n<li>Dual Priority encoder<\/li>\n<li>Cascading comparators<\/li>\n<\/ul>\n<p><strong>UNIT &#8211; V : Subsystem Design using Functional Blocks (2):<\/strong> Design, (including Timing Analysis) of different logical blocks of different complexities involving mostly sequential circuits:<\/p>\n<ul>\n<li>Pattern (sequence) detector<\/li>\n<li>Programmable Up-down counter<\/li>\n<li>Round robin arbiter with 3 requesters<\/li>\n<li>Process Controller<\/li>\n<li>FIFO<\/li>\n<\/ul>\n<p><strong>TEXT BOOKS:<\/strong><\/p>\n<ul>\n<li>John F. Wakerly, \u201cDigital Design\u201d, Prentice Hall, 3rd Edition, 2002<\/li>\n<\/ul>\n<p><strong>*Note1:<\/strong> VHDL and ABEL are not part of this course.<br \/>\n<strong>*Note2:<\/strong> SSI &amp; MSI ICs listed in data books are not part of this course<\/p>\n<p>For all other M.Tech 1st Year 1st Sem syllabus go to <a href=\"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-first-year-first-sem-vlsi-vlsi-design-vlsi-system-design-for-m-tech-2017-2018-r17-batch\/\">JNTUH M.Tech VLSI\/ VLSI Design\/VLSI System Design 1st Year 1st Sem Course Structure for (R17) Batch.<\/a><\/p>\n<p>All details and yearly new syllabus will be updated here time to time. Subscribe, like us on facebook and follow us on google plus for all updates.<\/p>\n<p>Do share with friends and in case of questions please feel free drop a comment.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Advanced Digital System Design Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and [&hellip;]<\/p>\n","protected":false},"author":2259,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[73,62],"tags":[],"class_list":["post-8984","post","type-post","status-publish","format-standard","hentry","category-m-tech","category-syllabus"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/8984","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/users\/2259"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/comments?post=8984"}],"version-history":[{"count":2,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/8984\/revisions"}],"predecessor-version":[{"id":13933,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/8984\/revisions\/13933"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/media?parent=8984"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/categories?post=8984"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/tags?post=8984"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}