{"id":23390,"date":"2020-07-16T13:34:03","date_gmt":"2020-07-16T13:34:03","guid":{"rendered":"https:\/\/www.inspirenignite.com\/jntuh\/ec603pc-vlsi-design-ece-syllabus-for-btech-3rd-year-2nd-sem-r18-regulation-jntuh\/"},"modified":"2020-07-16T13:34:03","modified_gmt":"2020-07-16T13:34:03","slug":"ec603pc-vlsi-design-ece-syllabus-for-btech-3rd-year-2nd-sem-r18-regulation-jntuh","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuh\/ec603pc-vlsi-design-ece-syllabus-for-btech-3rd-year-2nd-sem-r18-regulation-jntuh\/","title":{"rendered":"EC603PC: Vlsi Design ECE Syllabus for B.Tech 3rd Year 2nd Sem R18 Regulation JNTUH"},"content":{"rendered":"

Vlsi Design detailed Syllabus for Electronics & Communication Engineering (ECE), R18 regulation has been taken from the JNTUH<\/a> official website and presented for the students affiliated to JNTUH course structure. For Course Code, Subject Names, Theory Lectures, Tutorial, Practical\/Drawing, Credits, and other information do visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the universities official website.<\/p>\n

For all other ECE 3rd Year 2nd Sem Syllabus for B.Tech R18 Regulation JNTUH, do visit ECE 3rd Year 2nd Sem Syllabus for B.Tech R18 Regulation JNTUH <\/a>Subjects. The detailed Syllabus for vlsi design is as follows. <\/p>\n

Pre-requisite:<\/h4>\n

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App<\/a>
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.<\/b>
\"Get<\/a>. <\/p>\n

Course Objectives:<\/h4>\n

\nThe objectives of the course are to:<\/p>\n

    \n
  1. Give exposure to different steps involved in the fabrication of ICs.<\/li>\n
  2. Explain electrical properties of MOS and BiCMOS devices to analyze the behavior of inverters designed with various loads.<\/li>\n
  3. Give exposure to the design rules to be followed to draw the layout of any logic circuit.<\/li>\n
  4. Provide design concepts to design building blocks of data path of any system using gates.<\/li>\n
  5. Understand basic programmable logic devices and testing of CMOS circuits.<\/li>\n<\/ol>\n

    Course Outcomes:<\/h4>\n

    \nUpon completing this course, the student will be able to<\/p>\n

      \n
    1. Acquire qualitative knowledge about the fabrication process of integrated circuits using MOS transistors.<\/li>\n
    2. Draw the layout of any logic circuit which helps to understand and estimate parasitic effect of any logic circuit<\/li>\n
    3. Design building blocks of data path systems, memories and simple logic circuits using PLA, PAL, FPGA and CPLD.<\/li>\n
    4. Understand different types of faults that can occur in a system and learn the concept of testing and adding extra hardware to improve testability of system.<\/li>\n<\/ol>\n

      Unit I<\/h4>\n

      For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App<\/a>
      It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.<\/b>
      \"Get<\/a>. <\/p>\n

      Unit II<\/h4>\n

      \nVLSI Circuit Design Processes: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits.<\/p>\n

      Unit III<\/h4>\n

      \nGate Level Design: Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time delays, Driving large capacitive loads, Wiring capacitance, Fan – in, Fan – out.<\/p>\n

      Unit IV<\/h4>\n

      For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App<\/a>
      It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.<\/b>
      \"Get<\/a>. <\/p>\n

      Unit V<\/h4>\n

      \nProgrammable Logic Devices: Design Approach – PLA, PAL, Standard Cells FPGAs, CPLDs.<\/p>\n

      CMOS Testing: CMOS Testing, Test Principles, Design Strategies for test, Chip level Test Techniques.<\/p>\n

      Text Books:<\/h4>\n

      \n

        \n
      1. Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian Dougles and A.Pucknell, PHI, 2005 Edition<\/li>\n
      2. CMOS VLSI Design – A Circuits and Systems Perspective, Neil H. E Weste, David Harris, Ayan Banerjee, 3rd Ed, Pearson, 2009.<\/li>\n<\/ol>\n

        Reference Book:<\/h4>\n

        For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App<\/a>
        It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.<\/b>
        \"Get<\/a>.<\/p>\n

        For detail Syllabus of all other subjects of B.Tech 3rd Year Electronics & Communication Engineering, visit ECE 3rd Year Syllabus<\/a> Subjects.<\/p>\n

        For all B.Tech results, visit JNTUH B.Tech all years, and semester results <\/a>from direct links.<\/p>\n","protected":false},"excerpt":{"rendered":"

        Vlsi Design detailed Syllabus for Electronics & Communication Engineering (ECE), R18 regulation has been taken from the JNTUH official website and presented for the students affiliated to JNTUH course structure. […]<\/p>\n","protected":false},"author":2344,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[122,3],"tags":[],"class_list":["post-23390","post","type-post","status-publish","format-standard","hentry","category-3rd-year","category-ece"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/23390","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/users\/2344"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/comments?post=23390"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/23390\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/media?parent=23390"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/categories?post=23390"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/tags?post=23390"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}