System on Chip Architecture Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year second sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.<\/p>\n
The detailed syllabus for System on Chip Architecture M.Tech 2017-2018 (R17) first year second sem is as follows.<\/p>\n
M.Tech. I Year II Sem.<\/p>\n
UNIT \u2013 I : Introduction to the System Approach:<\/strong> System Architecture, Components of the system, Hardware & Software, Processor Architectures, Memory, and Addressing. System level interconnection, An approach for SOC Design, System Architecture and Complexity.<\/p>\n UNIT \u2013 II : Processors<\/strong>: Introduction , Processor Selection for SOC, Basic concepts in Processor Architecture, Basic concepts in Processor Micro Architecture, Basic elements in Instruction handling. Buffers: minimizing Pipeline Delays, Branches, More Robust Processors, Vector Processors and Vector Instructions extensions, VLIW Processors, Superscalar Processors.<\/p>\n UNIT \u2013 III : Memory Design for SOC:<\/strong> Overview of SOC external memory, Internal Memory, Size, Scratchpads and Cache memory, Cache Organization, Cache data, Write Policies, Strategies for line replacement at miss time, Types of Cache, Split \u2013 I, and D \u2013 Caches, Multilevel Caches, Virtual to real translation , SOC Memory System, Models of Simple Processor \u2013 memory interaction.<\/p>\n UNIT – IV : Interconnect Customization and Configuration:<\/strong> Inter Connect Architectures, Bus: Basic Architectures, SOC Standard Buses , Analytic Bus Models, Using the Bus model, Effects of Bus transactions and contention time. SOC Customization: An overview, Customizing Instruction Processor, Reconfiguration Technologies, Mapping design onto Reconfigurable devices, InstanceSpecific design, Customizable Soft Processor, Reconfiguration – overhead analysis and trade-off analysis on reconfigurable Parallelism.<\/p>\n UNIT \u2013 V : Application Studies \/ Case Studies:<\/strong> SOC Design approach, AES algorithms, Design and evaluation, Image compression \u2013 JPEG compression.<\/p>\n TEXT BOOKS:<\/strong><\/p>\n REFERENCE BOOKS:<\/strong><\/p>\n\n
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