{"id":13041,"date":"2018-09-25T13:38:20","date_gmt":"2018-09-25T13:38:20","guid":{"rendered":"https:\/\/www.inspirenignite.com\/jntuh\/?p=13041"},"modified":"2026-05-24T10:23:54","modified_gmt":"2026-05-24T04:53:54","slug":"jntuh-m-tech-2017-2018-r17-detailed-syllabus-vlsi-and-dsp-architectures","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-m-tech-2017-2018-r17-detailed-syllabus-vlsi-and-dsp-architectures\/","title":{"rendered":"JNTUH M.Tech 2017-2018 (R17) Detailed Syllabus VLSI and DSP Architectures"},"content":{"rendered":"VLSI and DSP Architectures Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year second sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.\r\n\r\nThe detailed syllabus for VLSI and DSP Architectures M.Tech 2017-2018 (R17) first year second sem is as follows.\r\n\r\nM.Tech. I Year II Sem.\r\n\r\nUNIT – I : Essential feature<\/strong> of Instruction set architectures of CISC, RISC and DSP processors and their implications for implementation as VLSI Chips, Micro programming approaches for implementation of control part of the processor. Assessing understanding performance, Introduction, CPU performance and its factors, evaluating performance, real stuff: Two spec bench marks and performance of recent INTEL processors, fallacies and pitfalls\r\n\r\nUNIT – II : Data Path and Control:<\/strong> Introduction, logic design conventions, building a data path, a simple implementation scheme, a multi cycle implementation, exceptions, micro programming: simplifying control design, an introduction to digital design using hardware description language, fallacies and pitfalls\r\n\r\nUNIT – III : Enhancing performance with pipeline:<\/strong> An overview of pipelining, a pipe lined data path. Pipe lined control, data hazards and forwarding, data hazards and stalls, branch hazards using a hard ware description language to describe and model a pipe line, exceptions, advanced pipelining: extracting more performance, fallacies and pitfalls\r\n\r\nUNIT – IV : Computational Accuracy in DSP implementations<\/strong>: Introduction, number formats for signals and coefficients in DSP system, dynamic range and precision, sources of errors in DSP implementations, A\/D conversion errors, DSP computational errors, D \/A conversion errors\r\n\r\nUNIT – V : Architectures for programmable digital signal processing devices:<\/strong> Introduction, basic architectural features, DSP Computational building blocks, bus architecture and memory, data addressing capabilities, address generation unit, programmability and program execution, speed issues, features for external interfacing.\r\n\r\nTEXT BOOKS:<\/strong>\r\n