{"id":13037,"date":"2018-09-25T13:30:32","date_gmt":"2018-09-25T13:30:32","guid":{"rendered":"https:\/\/www.inspirenignite.com\/jntuh\/?p=13037"},"modified":"2026-05-24T10:23:57","modified_gmt":"2026-05-24T04:53:57","slug":"jntuh-m-tech-2017-2018-r17-detailed-syllabus-design-for-testability","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-m-tech-2017-2018-r17-detailed-syllabus-design-for-testability\/","title":{"rendered":"JNTUH M.Tech 2017-2018 (R17) Detailed Syllabus Design for Testability"},"content":{"rendered":"Design for Testability Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year second sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.\r\n\r\nThe detailed syllabus for Design for Testability M.Tech 2017-2018 (R17) first year second sem is as follows.\r\n\r\nM.Tech. I Year II Sem.\r\n\r\n<strong>UNIT &#8211; I : Introduction to Testing:<\/strong> Testing Philosophy, Role of Testing, Digital and Analog VLSI Testing, VLSI Technology Trends affecting Testing, Types of Testing, Fault Modeling: Defects, Errors and Faults, Functional Versus Structural Testing, Levels of Fault Models, Single Stuck-at Fault.\r\n\r\n<strong>UNIT &#8211; II : Logic and Fault Simulation:<\/strong> Simulation for Design Verification and Test Evaluation, Modeling Circuits for Simulation, Algorithms for True-value Simulation, Algorithms for Fault Simulation, ATPG.\r\n\r\n<strong>UNIT &#8211; III : Testability Measures:<\/strong> SCOAP Controllability and Observability, High Level Testability Measures, Digital DFT and Scan Design: Ad-Hoc DFT Methods, Scan Design, Partial-Scan Design, Variations of Scan.\r\n\r\n<strong>UNIT &#8211; IV : Built-In Self-Test:<\/strong> The Economic Case for BIST, Random Logic BIST: Definitions, BIST Process, Pattern Generation, Response Compaction, Built-In Logic Block Observers, Test-Per-Clock, Test-PerScan BIST Systems, Circular Self Test Path System, Memory BIST, Delay Fault BIST.\r\n\r\n<strong>UNIT &#8211; V : Boundary Scan Standard:<\/strong> Motivation, System Configuration with Boundary Scan: TAP Controller and Port, Boundary Scan Test Instructions, Pin Constraints of the Standard, Boundary Scan Description Language: BDSL Description Components, Pin Descriptions.\r\n\r\n<strong>TEXT BOOK:<\/strong>\r\n<ul>\r\n \t<li>M.L. Bushnell, V. D. Agrawal, \u201cEssentials of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits\u201d Kluwer Academic Publishers.<\/li>\r\n<\/ul>\r\n<strong>REFERENCE BOOKS<\/strong>:\r\n<ul>\r\n \t<li>M. Abramovici, M. A. Breuer and A.D Friedman, \u201cDigital Systems and Testable Design\u201d, Jaico Publishing House.<\/li>\r\n \t<li>P.K. Lala, \u201cDigital Circuits Testing and Testability\u201d, Academic Press.<\/li>\r\n<\/ul>\r\nFor all other M.Tech 1st Year 2nd Sem syllabus go to <a href=\"https:\/\/www.inspirenignite.com\/jntuh\/jntuh-first-year-second-sem-vlsi-vlsi-design-vlsi-system-design-for-m-tech-2017-2018-r17-batch\/\">JNTUH M.Tech VLSI\/ VLSI Design\/VLSI System Design 1st Year 2nd Sem Course Structure for (R17) Batch.<\/a>\r\n\r\nAll details and yearly new syllabus will be updated here time to time. Subscribe, like us on facebook and follow us on google plus for all updates.\r\n\r\nDo share with friends and in case of questions please feel free drop a comment.\n\n<h2>Download iStudy App (Android &amp; iOS)<\/h2>\n<div style=\"width: 100%;text-align: center;background: #f0f7ff;border: 1px solid #d9e8ff;border-radius: 10px;padding: 12px 10px;margin: 8px 0 12px 0\">\n<p style=\"margin: 0 0 8px 0\">Get instant JNTUH updates, timetables, results, and notices on mobile.<\/p>\n<div style=\"justify-content: center;align-items: flex-start;gap: 24px;flex-wrap: wrap\">\n<div style=\"flex-direction: column;align-items: center;gap: 2px\"><img decoding=\"async\" style=\"height: 54px;width: auto\" src=\"https:\/\/play.google.com\/intl\/en_us\/badges\/static\/images\/badges\/en_badge_web_generic.png\" alt=\"Get it on Google Play\" \/>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\u00a0<img decoding=\"async\" style=\"height: 80px;width: 80px\" src=\"https:\/\/api.qrserver.com\/v1\/create-qr-code\/?size=120x120&amp;data=https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" alt=\"Android app QR code\" \/><\/div>\n<div>\u00a0<\/div>\n<div style=\"flex-direction: column;align-items: center;gap: 2px\"><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">Android App<\/a><\/div>\n<div>\u00a0<\/div>\n<div style=\"flex-direction: column;align-items: center;gap: 2px\"><img decoding=\"async\" style=\"height: 40px;width: auto\" src=\"https:\/\/upload.wikimedia.org\/wikipedia\/commons\/3\/3c\/Download_on_the_App_Store_Badge.svg\" alt=\"Download on the App Store\" \/>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\u00a0<img decoding=\"async\" style=\"height: 80px;width: 80px\" src=\"https:\/\/api.qrserver.com\/v1\/create-qr-code\/?size=120x120&amp;data=https:\/\/apps.apple.com\/us\/app\/istudy-app-syllabus-papers\/id6478500231\" alt=\"iOS app QR code\" \/><\/div>\n<div>\u00a0<\/div>\n<div style=\"flex-direction: column;align-items: center;gap: 2px\"><a href=\"https:\/\/apps.apple.com\/us\/app\/istudy-app-syllabus-papers\/id6478500231\" target=\"_blank\" rel=\"noopener\">iOS App <\/a><\/div>\n<\/div>\n<\/div>\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Design for Testability Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year second sem is covered here. This gives the details about credits, number of hours and other [&hellip;]<\/p>\n","protected":false},"author":2259,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[73,62],"tags":[],"class_list":["post-13037","post","type-post","status-publish","format-standard","hentry","category-m-tech","category-syllabus"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/13037","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/users\/2259"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/comments?post=13037"}],"version-history":[{"count":3,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/13037\/revisions"}],"predecessor-version":[{"id":39326,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/posts\/13037\/revisions\/39326"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/media?parent=13037"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/categories?post=13037"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/jntuh\/wp-json\/wp\/v2\/tags?post=13037"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}