Design for Testability Detailed Syllabus for VLSI\/ VLSI Design\/VLSI System Design M.Tech first year second sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.<\/p>\n
The detailed syllabus for Design for Testability M.Tech 2017-2018 (R17) first year second sem is as follows.<\/p>\n
M.Tech. I Year II Sem.<\/p>\n
UNIT – I : Introduction to Testing:<\/strong> Testing Philosophy, Role of Testing, Digital and Analog VLSI Testing, VLSI Technology Trends affecting Testing, Types of Testing, Fault Modeling: Defects, Errors and Faults, Functional Versus Structural Testing, Levels of Fault Models, Single Stuck-at Fault.<\/p>\n UNIT – II : Logic and Fault Simulation:<\/strong> Simulation for Design Verification and Test Evaluation, Modeling Circuits for Simulation, Algorithms for True-value Simulation, Algorithms for Fault Simulation, ATPG.<\/p>\n UNIT – III : Testability Measures:<\/strong> SCOAP Controllability and Observability, High Level Testability Measures, Digital DFT and Scan Design: Ad-Hoc DFT Methods, Scan Design, Partial-Scan Design, Variations of Scan.<\/p>\n UNIT – IV : Built-In Self-Test:<\/strong> The Economic Case for BIST, Random Logic BIST: Definitions, BIST Process, Pattern Generation, Response Compaction, Built-In Logic Block Observers, Test-Per-Clock, Test-PerScan BIST Systems, Circular Self Test Path System, Memory BIST, Delay Fault BIST.<\/p>\n UNIT – V : Boundary Scan Standard:<\/strong> Motivation, System Configuration with Boundary Scan: TAP Controller and Port, Boundary Scan Test Instructions, Pin Constraints of the Standard, Boundary Scan Description Language: BDSL Description Components, Pin Descriptions.<\/p>\n TEXT BOOK:<\/strong><\/p>\n REFERENCE BOOKS<\/strong>:<\/p>\n\n
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